XR16L784_08 Datasheet, PDF (51/51 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART

XR16L784
REV. 1.2.3
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
TABLE 10: TIMER CONTROL REGISTER ........................................................................................................................................ 22
3.1.3 8XMODE [7:0] (default 0x00) ..................................................................................................................................... 23
3.1.4 REGA [7:0] reserved (default 0x00) .......................................................................................................................... 23
3.1.5 RESET [7:0] (default 0x00) ......................................................................................................................................... 23
3.1.6 SLEEP [7:0] - (default 0x00) ....................................................................................................................................... 24
3.1.7 Device Identification and Revision ............................................................................................................................ 24
3.1.8 REGB [7:0] - (default 0x00) ......................................................................................................................................... 24
3.2 UART CHANNEL CONFIGURATION REGISTERS .......................................................................................... 25
TABLE 11: UART CHANNEL CONFIGURATION REGISTERS ...................................................................................................... 25
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. .......... 26
4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................. 27
4.1 RECEIVE HOLDING REGISTER (RHR) - READ ONLY ................................................................................... 27
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ................................................................................ 27
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................. 27
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION .............................................................................. 27
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ................................................................. 27
4.4 INTERRUPT STATUS REGISTER (ISR) - READ ONLY ................................................................................... 28
4.4.1 INTERRUPT GENERATION: ....................................................................................................................................... 29
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................ 29
TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 29
4.5 FIFO CONTROL REGISTER (FCR) - WRITE ONLY ......................................................................................... 30
TABLE 14: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION ............................................................................. 31
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ......................................................................................... 31
TABLE 15: PARITY SELECTION .......................................................................................................................................................... 32
4.7 MODEM CONTROL REGISTER (MCR) - READ/WRITE .................................................................................. 33
4.8 LINE STATUS REGISTER (LSR) - READ ONLY .............................................................................................. 34
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 34
4.10 MODEM STATUS REGISTER (MSR) - WRITE ONLY .................................................................................... 35
TABLE 16: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE ................................................... 36
4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 36
4.12 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ............................................................................ 36
TABLE 17: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED ................................................................... 37
4.13 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 38
TABLE 18: SOFTWARE FLOW CONTROL FUNCTIONS .......................................................................................................................... 38
4.14 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ ONLY ................................................................ 39
4.15 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE ONLY ............................................................... 39
4.16 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ ONLY ................................................................... 39
4.17 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE ONLY ................................................................... 39
TABLE 19: UART RESET CONDITIONS ........................................................................................................................................ 40
ABSOLUTE MAXIMUM RATINGS ................................................................................ 41
ELECTRICAL CHARACTERIISTICS ............................................................................. 41
DC ELECTRICAL CHARACTERISTICS ............................................................................................... 41
Figure 16. XR16L784 VOL Sink Current Chart ............................................................................................................................ 42
Figure 17. XR16L784 VOH Source Current Chart ....................................................................................................................... 42
AC ELECTRICAL CHARACTERISTICS ............................................................................................... 43
Figure 18. 16 Mode (Intel) Data Bus Read and Write Timing ...................................................................................................... 44
Figure 19. 68 Mode (Motorola) Data Bus Read and Write Timing ............................................................................................... 45
Figure 20. Modem Input/Output Port Delay ................................................................................................................................. 46
Figure 21. Receive Interrupt Timing [Non-FIFO Mode] ................................................................................................................ 46
Figure 22. Transmit Interrupt Timing [Non-FIFO Mode] ............................................................................................................... 47
Figure 23. Receive Interrupt Timing [FIFO Mode] ....................................................................................................................... 47
Figure 24. Transmit Interrupt Timing [FIFO Mode] ...................................................................................................................... 47
PACKAGE DIMENSIONS, 64-LQFP ............................................................................. 48
REVISION HISTORY .................................................................................................................................. 49
TABLE OF CONTENTS .................................................................................................... I
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