XR16L784_08 Datasheet, PDF (21/51 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART

XR16L784
REV. 1.2.3
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
3.1.1 The Global Interrupt Source Registers
The XR16L784 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1,
INT2 and INT3]. Register INT3 is not used in the 784 UART, only in the 8-channel XR16L788. The 3 registers
are in the device configuration register address space.
INT3 (Rsvd)
[0x00]
INT2
[0x00]
INT1
[0x00]
INT0
[0x00]
All 4 registers default to logic zero (as indicated in square braces) for no interrupt pending. All 4 channel
interrupts are enabled or disabled in each channel’s IER register. INT0 shows individual status for each
channel while INT1 and INT2 show the details of the source of each channel’s interrupt with its unique 3-bit
encoding. Figure 14 shows the 4 interrupt registers in sequence for clarity. The 16-bit timer and sleep wake-
up interrupts are masked in the device configuration registers, TIMERCNTL and SLEEP. An interrupt is
generated by the 784 when awakened from sleep if all 4 channels were placed in the sleep mode previously.
Reading INT0 will clear this wake-up interrupt.
Each bit in the INT0 register gives an indication of the channel that has requested service.
3.1.1.1
INT0 Channel Interrupt Indicator:
INT0 Register
Individual UART Channel Interrupt Status
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Rsvd Rsvd Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0
For example, bit-0 represents channel 0 and bit-3 indicates channel 3. Bits 4 to 7 are reserved and remains at
logic zero. Logic one indicates the channel N [3:0] has called for service. The interrupt bit clears after reading
the appropiate register of the interrupting UART channel register (ISR, LSR and MSR). See Table 13 for
interrupt clearing details.
3.1.1.2
INT1 and INT2 Interrupt Source Locator
INT2 and INT1 provide a 12-bit (3 bits per channel) encoded interrupt indicator. Table 9 shows the 3 bit
encoding and their priority order. The 16-bit Timer time-out interrupt will show up only as a channel 0 interrupt .
For other channels, interrupt 7 is reserved.
.
FIGURE 14. THE GLOBAL INTERRUPT REGISTERS, INT0, INT1, INT2 AND INT3
Interrupt Registers,
INT0, INT1, INT2 and INT3
INT3 Register
INT2 Register
INT1 Register
Reserved
Bit Bit Bit
21
0
Reserved
Bit Bit Bit
2
1
0
Reserved
Bit Bit Bit
21
0
Reserved
Bit Bit Bit
21
0
Channel-3
Bit Bit Bit
2
1
0
Channel-2
Bit Bit Bit
21
0
Channel-1
Bit Bit Bit
21
0
Channel-0
Bit Bit Bit
2
1
0
INT0 Register
Rsvd Rsvd Rsvd Rsvd Ch-3 Ch-2 Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
21