XR16L788IQ-F Datasheet, PDF (53/54 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART

REV. 1.2.3
XR16L788
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
TABLE OF CONTENTS
GENERAL DESCRIPTION ............................................................................................... 1
APPLICATIONS ........................................................................................................................................... 1
FEATURES ................................................................................................................................................ 1
FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1
FIGURE 2. PIN OUT OF THE DEVICE ................................................................................................................................................. 2
ORDERING INFORMATION ........................................................................................................................... 2
PIN DESCRIPTIONS ....................................................................................................... 3
1.0 DESCRIPTION ........................................................................................................................................ 7
2.0 Functional Descriptions ........................................................................................................................ 7
2.1 DEVICE RESET ................................................................................................................................................... 7
2.2 UART CHANNEL SELECTION .......................................................................................................................... 7
TABLE 1: UART CHANNEL SELECTION ............................................................................................................................................ 7
2.3 SIMULTANEOUS WRITE TO ALL CHANNELS ................................................................................................ 7
2.4 INT# OUPUT ....................................................................................................................................................... 8
TABLE 2: INT# PIN OPERATION FOR TRANSMITTER .......................................................................................................................... 8
TABLE 3: INT# PIN OPERATION FOR RECEIVER ............................................................................................................................... 8
2.5 CRYSTAL OSCILLATOR / BUFFER .................................................................................................................. 8
Figure 3. Typical oscillator connections ........................................................................................................................................ 8
2.6 PROGRAMMABLE BAUD RATE GENERATOR ............................................................................................... 9
Figure 4. External Clock Connection for Extended Data Rate ..................................................................................................... 9
Figure 5. Baud Rate Generator ..................................................................................................................................................... 9
TABLE 4: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ......................................... 10
2.7 TRANSMITTER ................................................................................................................................................. 10
Figure 6. Transmitter Operation in non-FIFO Mode ................................................................................................................... 11
Figure 7. Transmitter Operation in FIFO and Flow Control Mode ............................................................................................... 11
2.8 RECEIVER ........................................................................................................................................................ 11
Figure 8. Receiver Operation in non-FIFO Mode ....................................................................................................................... 12
Figure 9. Receiver Operation in FIFO and Auto RTS Flow Control Mode .................................................................................. 12
2.9 THR AND RHR REGISTER LOCATIONS ........................................................................................................ 13
TABLE 5: TRANSMIT AND RECEIVE HOLDING REGISTER LOCATIONS, 16C550 COMPATIBLE .............................................................. 13
2.10 AUTOMATIC RTS/DTR HARDWARE FLOW CONTROL OPERATION ....................................................... 13
Figure 10. Auto RTS/DTR and CTS/DSR Flow Control Operation ............................................................................................. 15
2.11 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ..................................................................................... 16
TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 16
2.12 SPECIAL CHARACTER DETECT ................................................................................................................. 16
2.13 AUTO RS485 HALF-DUPLEX CONTROL .................................................................................................... 16
2.14 INFRARED MODE .......................................................................................................................................... 17
Figure 11. Infrared Transmit Data Encoding and Receive Data Decoding ................................................................................. 17
2.15 SLEEP MODE WITH AUTO WAKE-UP ........................................................................................................ 18
2.16 INTERNAL LOOPBACK ................................................................................................................................. 19
Figure 12. Internal Loop Back .................................................................................................................................................... 19
3.0 XR16L788 REGISTERS ....................................................................................................................... 20
Figure 13. The XR16L788 Registers .......................................................................................................................................... 20
3.1 DEVICE CONFIGURATION REGISTER SET ................................................................................................... 20
TABLE 7: XR16L788 REGISTER SETS ........................................................................................................................................... 20
TABLE 8: DEVICE CONFIGURATION REGISTERS .............................................................................................................................. 21
Figure 14. The Global Interrupt Registers, INT0, INT1, INT2 and INT3 ..................................................................................... 22
TABLE 9: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING AND CLEARING ............................................................................. 23
Figure 15. Timer/Counter circuit ................................................................................................................................................. 23
TABLE 10: TIMER CONTROL REGISTER ..................................................................................................................................... 24
3.2 UART CHANNEL CONFIGURATION REGISTERS ......................................................................................... 27
TABLE 11: UART CHANNEL CONFIGURATION REGISTERS ................................................................................................... 27
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ....... 28
4.0 Internal Register Descriptions ........................................................................................................... 29
4.1 RECEIVE HOLDING REGISTER (RHR) - READ ONLY .................................................................................. 29
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY .............................................................................. 29
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................... 29
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