XR16L788IQ-F Datasheet, PDF (13/54 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART

XR16L788
REV. 1.2.3
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
2.9 THR and RHR Register Locations
The THR and RHR register addresses for channel 0 to channel 7 is shown in Table 5 below. The THR and
RHR for channels 0 to 7 are located at address 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60 and 0x70
respectively. Transmit data byte is loaded to the THR when writing to that address and receive data is
unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550
compatible in 8-bit format, so each bus operation can only write or read in bytes.
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TABLE 5: TRANSMIT AND RECEIVE HOLDING REGISTER LOCATIONS, 16C550 COMPATIBLE
THR and RHR Address Locations For CH0 to CH7 (16C550 Compatible)
CH0 0x00 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH0 0x00 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH1 0x10 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH1 0x10 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH2 0x20 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH2 0x20 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH3 0x30 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH3 0x30 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH4 0x40 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH4 0x40 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH5 0x50 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH5 0x50 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH6 0x60 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH6 0x60 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH7 0x70 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH7 0x70 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
THRRHR1
2.10 Automatic RTS/DTR Hardware Flow Control Operation
Automatic RTS/DTR flow control is used to prevent data overrun to the local receiver FIFO. The RTS#/DTR#
output pin is used to request remote unit to suspend/resume data transmission. The flow control features are
individually selected to fit specific application requirement (see Figure 10):
• Select RTS (and CTS) or DTR (and DSR) through MCR bit-2.
• Enable auto RTS/DTR flow control using EFR bit-6.
• The auto RTS or auto DTR function must be started by asserting the RTS# or DTR# output pin (MCR bit-1 or
bit-0 to a logic 1, respectively) after it is enabled.
• If using programmable RX FIFO trigger levels, hysteresis levels can be selected via FCTR bits 3-0.
With the Auto RTS function enabled, the RTS# output pin will not be de-asserted (HIGH) when the receive
FIFO reaches the programmed trigger level, but will be de-asserted when the FIFO reaches the next trigger
level for Trigger Tables A-C (See Table 14). The RTS# output pin will be asserted (LOW) again after the FIFO
is unloaded to the next trigger level below the programmed trigger level.
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