XR16L788IQ-F Datasheet, PDF (40/54 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART

XR16L788
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
REV. 1.2.3
FCTR[7:6]: TX and RX FIFO Trigger Table Select
These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is
selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550
and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one
FIFO level above and one FIFO level below. See in Table 14 for complete selection with FCR bit 4-5 and FCTR
bit 6-7, i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR# output will
de-assert at 60 and re-assert at 16.
4.13 Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 18). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR BIT-3
CONT-3
0
0
1
0
1
X
X
X
1
0
1
0
TABLE 18: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
0
0
No TX and RX flow control (default and reset)
0
X
X
No transmit flow control
0
X
X
Transmit Xon1/Xoff1
1
X
X
Transmit Xon2/Xoff2
1
X
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
0
0
No receive flow control
X
1
0
Receiver compares Xon1/Xoff1
X
0
1
Receiver compares Xon2/Xoff2
0
1
1
Transmit Xon1/ Xoff1,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
Transmit Xon2/Xoff2,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
EFR[3:0]: Software Flow Control Select
Combinations of software flow control can be selected by programming these bits.
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