XR16L788IQ-F Datasheet, PDF (22/54 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART

XR16L788
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
REV. 1.2.3
3.1.1 The Global Interrupt Source Registers
The XR16L788 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1,
INT2 and INT3]. The four registers are in the device configuration register address space.
INT3
[0x00]
INT2
[0x00]
INT1
[0x00]
INT0
[0x00]
All four registers default to logic zero (as indicated in square braces) for no interrupt pending. All 8 channel
interrupts are enabled or disabled in each channel’s IER register. INT0 shows individual status for each
channel while INT1, INT2 and INT3 show the details of the source of each channel’s interrupt with its unique 3-
bit encoding. Figure 14 shows the 4 interrupt registers in sequence for clarity. The 16-bit timer and sleep
wake-up interrupts are masked in the device configuration registers, TIMERCNTL and SLEEP. An interrupt is
generated by the 788 when awakened from sleep if all 8 channels were placed in the sleep mode previously.
Reading INT0 will clear this wake-up interrupt.
Each bit gives an indication of the channel that has requested for service. For example, bit-0 represents
channel 0 and bit-7 indicates channel 7. Logic one indicates the channel N [7:0] has called for service. The
interrupt bit clears after reading the appropriate register of the interrupting UART channel register (ISR, LSR
and MSR). See Table 13 for interrupt clearing details.
3.1.1.1 INT0 Channel Interrupt Indicator:
INT0 Register
Individual UART Channel Interrupt Status
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
3.1.1.2 INT1, INT2 and INT3 Interrupt Source Locator
INT3, INT2 and INT1 provide a 24-bit (3 bits per channel) encoded interrupt indicator. Table 9 shows the 3 bit
encoding and their priority order. The 16-bit Timer time-out interrupt will show up only as a channel 0 interrupt.
For other channels, interrupt 7 is reserved.
.
FIGURE 14. THE GLOBAL INTERRUPT REGISTERS, INT0, INT1, INT2 AND INT3
Interrupt Registers,
INT0, INT1, INT2 and INT3
INT3 Register
INT2 Register
INT1 Register
Channel-7
Bit Bit Bit
21 0
Channel-6
Bit Bit Bit
21 0
Channel-5
Bit Bit Bit
21 0
Channel-4
Bit Bit Bit
21 0
Channel-3
Bit Bit Bit
21 0
Channel-2
Bit Bit Bit
21 0
Channel-1
Bit Bit Bit
21 0
Channel-0
Bit Bit Bit
21 0
INT0 Register
Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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