XRT75L04 Datasheet, PDF (46/57 Pages) Exar Corporation – FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 20: REGISTER MAP AND BIT NAMES - CHANNEL 3 REGISTERS
REV. 1.0.4
ADDRESS PARAMETER
DATA BITS
(HEX)
NAME
7
6
5
4
3
2
1
0
0x1D Receive Control
(read/write)
Reserved
DLOSDIS ALOSDIS RxClkINV LOSMUT_ RxMON_3 REQEN_3
_3
_3
_3
3
0x1E
Block Control
(read/write)
Reserved
PRBSEN_ RLB_3
3
LLB_3
E3_3
STS1/ SR/DR_3
DS3_3
0x1F Jitter Attenuator
(read/write)
Reserved
DFLCK_3 PNTRST_ JA1_3
3
JATx/
Rx_3
JA0_3
TABLE 21: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
REGISTER
TYPE
BIT#
NAME
SYMBOL
DESCRIPTION
DEFAULT
VALUE
D0 DMOIE_n Set this bit to enable an interrupt when the no trans-
0
mission detected on channel output.
D1 RLOSIE_n Writng a “1” to this bit enables an interrupt when
0
Recieve Los of Signal is detected.
D2 RLOLIE_n Writing a “1” to this bit enables an interrupt when
0
Receive Loss of Lock condition is detected
0x01 (ch 0) R/W Interrupt
D3 FLIE_n Writing a “1” to this bit enables the interrupt when
0
0x09 (ch 1)
0x11 (ch 2)
0x19 (ch 3)
Enable
(source
level)
the FIFO Limit of the Jitter Attenuator is within 2 bits
of overflow/underflow condition.
NOTE: This bit field is ignored when the Jitter
Attenuator is disabled.
D4 PRBSERIE Set this bit to enable the interrupt when the PRBS
0
_n
error is detected.
D5 PRBSERC Set this bit to enable the interrupt when the PRBS
0
NTIE_n error count register saturates.
D7-D6
Reserved
44