XRT75L04 Datasheet, PDF (41/57 Pages) Exar Corporation – FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

XRT75L04
REV. 1.0.4
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
signal (TxClk or RxClk) and clocked out of the FIFO with the dejittered clock. When the FIFO is within two bits
of overflowing or underflowing, the FIFO limit status bit, FL_n is set to “1” in the Alarm status register. Reading
this bit clears the FIFO and resets the bit into default state.
NOTE: It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts
of jitter. Table 13 specifies the jitter transfer mask requirements for various data rates:
TABLE 13: JITTER TRANSFER PASS MASKS
RATE
(KBITS)
MASK
F1
F2
F3
F4
A1(dB)
A2(dB)
(HZ)
(HZ)
(HZ)
(KHZ)
G.823
100
300
34368
ETSI-TBR-24
3K
800K
0.5
-19.5
44736
GR-499, Cat I
10
10k
-
15k
0.1
-
GR-499, Cat II
10
56.6k
-
300k
0.1
-
GR-253 CORE
10
40
-
15k
0.1
-
51840
GR-253 CORE
10
40k
-
400k
0.1
-
The jitter attenuator in the XRT75L04 meets the latest jitter attenuation specifications and/or jitter transfer
characteristics as shown in the Figure 24.
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE
A1
A2
F1
F2
F3
F4
JITTE R FR E Q U E N C Y (kH z)
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