XRT75L04 Datasheet, PDF (14/57 Pages) Exar Corporation – FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
OPERATING MODE SELECT
PIN #
SIGNAL NAME
TYPE
134
HOST/(HW)
I
92
E3_0
I
101
E3_1
129
E3_2
120
E3_3
93
STS-1/DS3_0
I
102
STS-1/DS3_1
128
STS-1/DS3_2
119
STS-1/DS3_3
136
SR/DR
I
DESCRIPTION
HOST/Hardware Mode Select:
Tie this pin “High” to configure in HOST mode. Tie this “Low” to configure in
Hardware mode.
When configured in HOST mode, the states of many of the discrete input pins
are controlled by internal register bits.
NOTE: This pin is internally pulled up.
E3 Mode Select Input
A "High" on this pin configures Channel_n to operate in E3 mode.
A "Low" on this pin configures Channel_n to operate in either STS-1 or DS3
mode depending on the settings on pins 93,102,128 and 119 pins.
NOTES:
1. This pin is internally pulled down
2. This pin is ignored and should be tied to GND if configured to operate
in HOST mode.
STS-1/DS3 Select Input
A “High” on these pins configures the Channel_n to operate in STS-1 mode.
A “Low” on these pins configures the Channel_n to operate in DS3 mode.
These pins are ignored if the E3_n pins are set to “High”.
NOTES:
1. This pin is internally pulled down
2. This pin is ignored and should be tied to GND if configured to operate
in HOST mode.
Single-Rail/Dual-Rail Select:
Setting this “High” configures both the Transmitter and Receiver to operate in
Single-rail mode and also enables the B3ZS/HDB3 Encoder and Decoder. In
Single-rail mode, TNEG_n pin should be grounded.
Setting this “Low” configures both the Transmitter and Receiver to operate in
Dual-rail mode and disables the B3ZS/HDB3 Encoder and Decoder.
NOTE: This pin is internally pulled down.
SERIAL MICROPROCESSOR INTERFACE
86
CS
RxCLKINV
I
Microprocessor Serial Interface - Chip Select
Toggle this pin “Low” to enable the communication with the Microprocessor
Serial Interface.( see figures 10 & 11)
NOTE: If configured in Hardware Mode, this pin functions as RxClkINV.
88
SClk
TxCLKINV
I
Serial Interface Clock Input
The data on the SDI pin is sampled on the rising edge of this signal. Addition-
ally, during Read operations the Microprocessor Serial Interface updates the
SDO output on the falling edge of this signal.
NOTE: If configured in Hardware Mode, this pin functions as TxClkINV.
12