XRT75L04 Datasheet, PDF (42/57 Pages) Exar Corporation – FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

XRT75L04
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.4
7.0 SERIAL HOST INTERFACE:
A serial microprocessor interface is included in the XRT75L04. The interface is generic and is designed to
support the common microprocessors/microcontrollers. The XRT75L04 operates in Host mode when the
HOST/HW pin is tied “High”. The serial interface includes a serial clock (SClk), serial data input (SDI), serial
data output (SDO), chip select (CS) and interrupt output (INT). The serial interface timing is shown in Figure
11.
The active low interrupt output signal (INT pin) indicates alarm conditions like LOS, DMO and FL to the
processor.
When the XRT75L04 is configured in Host mode, the following input pins,TxLEV_n, TAOS_n, RLB_n, LLB_n,
E3_n, STS-1/DS3_n, REQEN_n, JATx/Rx, JA0 and JA1 are disabled and must be connected to ground.
The Table 14 below illustrates the functions of the shared pins in either Host mode or in Hardware mode.
TABLE 14: FUNCTIONS OF SHARED PINS
PIN NUMBER
IN HOST MODE
IN HARDWARE MODE
86
CS
RxClkINV
88
SClk
TxClkINV
87
SDI
RxON
85
SDO
RxMON
84
INT
LOSMUT
NOTE: While configured in Host mode, the TxON_n input pins will be active if the TxON_n bits in the control register are set
to “1”, and can be used to turn on and off the transmit output drivers. This permits a system designed for
redundancy to quickly switch out a defective line card and switch-in the backup line card.
TABLE 15: REGISTER MAP AND BIT NAMES
ADDRESS
PARAMETER
DATA BITS
(HEX)
NAME
7
6
5
4
3
2
1
0
0x00 APS/Redundancy RxON-3 RxON-2 RxON-1 RxON_0 TxON_3 TxON_2 TxON_1 TxON_0
(read/write)
0x01-
0x1F
Channel 0 - 3 Control Registers
0x20
Interrupt Enable-
Global
(read/write)
Reserved
INTEN_3 INTEN_2 INTEN_1 INTEN_0
0x21
Interrupt Status
(read only)
Reserved
INTST_3 INTST_2 INTST_1 INTST_0
0x22-
0x2F
Reserved
Reserved
0x30 -
0x37
PRBS Count Registers
0x38
PRBS Holding Register
0x39 -
0x3D
Reserved
40