XRT79L73 Datasheet, PDF (45/71 Pages) Exar Corporation – 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L73
REV. P1.0.0
PIN #
AC12
AC16
AC8
NAME
RRING1
RRING2
RRING3
K2
CLKOUT1
G26
CLKOUT2
L3
CLKOUT3
TYPE
I
I
I
O
O
O
DESCRIPTION
Receive Input - Negative Polarity Signal:
These input pins, along the RTIPn input pins, function as the Receive DS3/E3
Line input signal receiver for the XRT79L73.
The user is expected to connect these signals and the RTIPn input signals to a
1:1 transformer.
Whenever the RTIP/RRING input pins are receiving a positive-polarity pulse
within the incoming DS3 or E3 line signal, then these input pins will be pulsed to
a "lower-voltage" than the RTIP input pins.
Conversely, whenever the RTIP/RRING input pins are receiving a negative-polar-
ity pulse within the incoming DS3 or E3 line signal, then these input pins will be
pulsed to a "higher-voltage" than the RTIP input pins.
SFM Synthesizer/Clock Recovery PLL Reference Clock Output:
The exact source of this output signal depends upon whether the XRT79L73
device has been configured to operate in the SFM (Single-Frequency Mode)
Mode, or not, as described below.If the XRT79L73 device is configured to oper-
ate in the SFM ModeIf the XRT79L73 device has been configured to operate in
the SFM Mode, then the CLKOUT output pin (if enabled) will output a
44.736MHz clock signal (if the XRT79L73 device is configured to operate in the
DS3 Mode) or a 34.368MHz clock signal (if the XRT79L73 device is configured to
operate in the E3 Mode.
NOTE: 1.In this case, the 44.736MHz or 33.368MHz clock (that is output via the
CLKOUT signal) will ultimately be derived from the 12.288MHz clock
signal that is being applied to the DS3CLK/SFMCLK input pin.
NOTE: 2.This output pin is only active if Bit 6 (SFM Clock Out Enable), within the
LIU Channel Control Register (Address = 0x1306) has been set to "1".
If the XRT79L73 device is NOT configured to operate in the SFM ModeIf the
XRT79L73 device has NOT been configured to operate in the SFM Mode, then
frequencies of the CLKOUT output signal will be as follows.
• If the XRT79L73 device has been configured to operate in the DS3 Mode, then
the XRT79L73 device will simply output a buffered version of the signal that is
being applied to the DS3CLK/SFMCLK input pin (which should be a
44.736MHz clock signal).
• If the XRT79L73 device has been configured to operate in the E3 Mode, then
the XRT79L73 device will simply output a buffered version of the signal that is
being applied to the E3CLK input pin (which should be a 34.368MHz clock
signal).
NOTE: This output pin is only if Bit 6 (SFM Clock Out Enable), within the "LIU
Channel Control" Register (Address = 0x1306) has been set to "1".
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