XRT79L73 Datasheet, PDF (26/71 Pages) Exar Corporation – 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L73
REV. P1.0.0
PRELIMINARY
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3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
PIN #
NAME
TYPE
DESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE PINS
M2
RxAIS1/
RxNib1_2/
RxHDLCDat1_2
H23
RxAIS2/
RxNib2_2/
RxHDLCDat2_2
P5
RxAIS3/
RxNib3_2/
RxHDLCDat3_2
O Receive AIS Pattern Indicator/Receive Nibble Output Interface - Bit 2/
Receive HDLC Controller Data Bus - Bit 2 output pin:
The function of these output pins depend upon whether the XRT79L73 has
O ^{been configured to operate in the Clear-Channel Framer/Nibble-Parallel Inter-}
face Mode, the High-Speed HDLC Controller Mode, or in the other modes.
Other Modes - RxAIS:
These output pins are driven "High" whenever the Receive Section of the
O
XRT79L73 has detected and is currently declaring an AIS (Alarm Indicator Sig-
nal) condition.
Clear-Channel Framer/Nibble-Parallel Interface Mode - RxNib_2:
If the XRT79L73 is configured to operate in the Nibble-Parallel Mode, then
these output pins will function as the bit 2 output from the Receive Nibble-Paral-
lel output interface. The Receive Payload Data Output Interface block will out-
put these signals (along with RxNibn_0, RxNibn_1, and RxNibn_3) upon the
rising edge of the RxClk output signals.
High-Speed HDLC Controller Mode - RxHDLCDat_2:
These output pins along with RxHDLCDatn_[7:3] and RxHDLCDatn_[1:0] func-
tions as the Receive HDLC Controller byte wide output data bus. The Receive
HDLC Controller will output the contents of all HDLC frames via this output data
bus, upon the rising edge of the RxHDLCClk output signals. Hence, the user's
local terminal equipment should be designed/configured to sample this data
upon the falling edge of the RxHDLCClk output clock signals.
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