XRT79L73 Datasheet, PDF (17/71 Pages) Exar Corporation – 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

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PRELIMINARY
3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT79L73
REV. P1.0.0
PIN #
AA2
V23
AC1
NAME
TxNib1_2/
TxStuff_Ctl1/
TxHDLCDat1_2
TxNib2_2/
TxStuff_Ctl2/
TxHDLCDat2_2
TxNib3_2/
TxStuff_Ctl3/
TxHDLCDat3_2
TYPE
I
I
I
DESCRIPTION
Transmit Nibble Input Interface - Bit 2/Transmit PLCP Stuff Control Input/
Transmit HDLC Controller Data Bus - Bit 2 Input:
The function of these input pins depend upon whether the XRT79L73 is config-
ured to operate in the Clear-Channel Framer Mode, the High-Speed HDLC Con-
troller Mode, or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxNib_2:
If the XRT79L73 is configured to operate in the Nibble-Parallel Mode, then these
input pins will function as the bit 1 input to the Transmit Nibble-Parallel input
interface. The Transmit Payload Data Input Interface block will sample these
signals (along with TxNibn_0, TxNibn_2 and TxNibn_3) upon the falling edge of
TxNibClk
NOTE: These input pins are inactive if the XRT79L73 is configured to operate in
the Serial Mode.
ATM/PLCP Mode - TxStuff_Ctl:
These input pins are used to externally exercise or forego trailer nibble stuffing
opportunities by the Transmit PLCP Processor. PLCP trailer nibble stuff oppor-
tunities occur in periods of three PLCP frames (375 us). The first PLCP frame
(first, within a stuff opportunity period) will have 13 trailer nibbles appended to it.
The second PLCP frame (second within a stuff opportunity period will have 14
trailer nibbles appended to it. The third PLCP frame (the location of the stuff
opportunity) will contain 13 trailer nibbles if thess input pins are pulled "Low", and
14 trailer nibbles if these input pins are pulled "High".
NOTE: These input pins are inactive if the XRT79L73 is configured to operate in
the Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_2:
If the XRT79L73 is configured to operate in the High-Speed HDLC Controller
mode, then the local terminal equipment will be provided with a byte-wide Trans-
mit HDLC Controller byte-wide input interface. These input pins will function as
Bit 1 within this byte wide interface.
Data, residing on the Transmit HDLC Controller byte wide input interface, will be
sampled upon the rising edge of the TxHDLCClk output signals.
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