XRT79L73 Datasheet, PDF (14/71 Pages) Exar Corporation – 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC

XRT79L73
REV. P1.0.0
PRELIMINARY
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3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
PIN #
F3
B25
H3
R1
M25
U1
NAME
TxPOHClk1
TxPOHClk2
TxPOHClk3
TxOHInd1/
TxPFrame1/
TxHDLCDat1_6
TxOHInd2/
TxPFrame2/
TxHDLCDat2_6
TxOHInd3/
TxPFrame3/
TxHDLCDat3_6
TYPE
DESCRIPTION
O Transmit PLCP Frame POH Byte Insertion Clock:
O These pins, along with the TxPOH and the TxPOHMSB input pins, function as
O ^{the Transmit PLCP Frame POH Byte serial input port. These output pins func-}
tion as clock output signals that are used to sample the user's POH data at the
TxPOH input pins. These output pins are always active, independent of the state
of the TxPOHIns pins.
NOTE: These pins are only active if the XRT79L73 has been configured to
operate in the ATM/PLCP Mode.
I/O Transmit Overhead Data Indicator Output/Transmit PLCP Frame Boundary
Indicator Output/Transmit HDLC Controller Data Bit 6 input pin:
The function of these input/output pins depends upon whether the XRT79L73
I/O ^{has been configured to operate in the Clear-Channel Framer Mode, the ATM/}
PLCP Mode or the High-Speed HDLC Mode.
Clear-Channel Framer Mode - TxOHInd:
I/O
In the Clear-Channel Framer Mode, these output pins function as the transmit
overhead data indicator for the local terminal equipment. These output pins are
pulsed "High" for one DS3 or E3 bit period in order to indicate to the local termi-
nal equipment that the Transmit Section of the Framer is going to be processing
an overhead bit, upon the next rising edge of TxInClk., and will NOT latch the
data that is applied to the TxSer input pins. Therefore, when the local terminal
equipment samples the TxOHInd output pin "High", then it must not apply the
next payload bit to TxSer input pin. These output pins serve as a warning that
this particular payload bit is going to be ignored by the Transmit Section of the
Framer, and will not be inserted into payload bits, within the outbound DS3 or E3
data stream.
ATM/PLCP Mode - TxPFrame:
If the XRT79L73 is configured to operate in the ATM UNI/PLCP Mode, then
these output pins will denote the boundaries of outbound PLCP frames, as they
are being processed by the Transmit PLCP Processor block. These outputs
pulse "High" when the last nibble of a given PLCP frame is being routed to the
Transmit DS3/E3 Framer block.
These output pins are inactive if the XRT79L73 is operating in the Direct-Mapped
ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_6:
If the XRT79L73 is configured to operate in the High-Speed HDLC Controller
mode, then the local terminal equipment will be provided with a byte-wide Trans-
mit HDLC Controller byte-wide input interface. These input pins will function as
Bit 6 within this byte wide interface.
Data, residing on the Transmit HDLC Controller byte wide input interface, will be
sampled upon the rising edge of the TxHDLCClk output signals.
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