ZADCS146_11 Datasheet, PDF (9/26 Pages) List of Unclassifed Manufacturers – 12-Bit, 200ksps, ADC Family

ZADCS146/147
12-Bit, 200ksps, ADC Family
1.3. Electrical Characteristics
1.3.1. General Parameters
(VDD = +2.7V to + 5.25V; f_SCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); V_REF = 2.500V applied to VREF pin; _OP = _OPmin …
 _OPmax)
Parameter
Symbol Conditions
Min
Typ Max Unit
DC Accuracy
Resolution
12
Bits
Relative Accuracy
INL
ZADCS146/ ZADCS147
 1.0 LSB
No Missing Codes
NMC
12
Bits
Differential Nonlinearity
DNL
ZADCS146/ ZADCS147
 1.0 LSB
Offset Error
 0.5  3.0 LSB
Gain Error
 0.5  4.0 LSB
Gain Temperature Coefficient
 0.25
ppm/°C
Dynamic Specifications (10kHz sine-wave input, 0V to 2.500Vpp, 200ksps, 3.2MHz external clock)
Signal-to-Noise + Distortion Ratio SINAD
Total Harmonic Distortion
THD
Up to the 5^th harmonic
68
73
dB
-88
-75
dB
Spurious-Free Dynamic Range SFDR
74
80
dB
Small-Signal Bandwidth
-3dB roll off
3.8
MHz
Conversion Rate
Sampling Time
(= Track/Hold Acquisition Time)
t _ACQ
Ext. Clock
acquisition
=
3.2MHz,
2.5
clocks/
0.758
µs
Conversion Time
t _CONV
Ext. Clock = 3.2MHz, 12 clocks/
conversion
Int. Clock = 3.2MHz +/- 12% tolerance 3.30
3.75 µs
4.20 µs
Aperture Delay
30
ns
Aperture Jitter
< 50
ps
External Clock Frequency
0.1
3.2 MHz
Internal Clock Frequency
2.81
3.2
3.58 MHz
Analog Inputs
Input Voltage Range, Single-
Ended and Differential
Input Capacitance
Unipolar, COM = 0V
Bipolar, COM = VREF/2
0 to VREF
V
 VREF / 2
16
pF
Data Sheet
October 12, 2011
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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