ZADCS146_11 Datasheet, PDF (21/26 Pages) List of Unclassifed Manufacturers – 12-Bit, 200ksps, ADC Family

ZADCS146/147
12-Bit, 200ksps, ADC Family
Output Code Format
ZADCS146 and ZADCS147 do support unipolar and bipolar operation modes. The digital output code is
straight binary in unipolar mode. It ranges from 0x00 for an input voltage difference of 0V to 0xFF for an input
voltage difference of VREF (Full Scale = FS). The first code transition (0x00  0x01) occurs at a voltage
equivalent to ½ LSB, the last (0xFE  0xFF) at VREF-1.5 LSB. See also Figure 14 for details. In bipolar
mode a two’s complement coding is applied. Code transitions occur again halfway between successive
integer LSB values. The transfer function is shown in Figure 15.
Output Code
11 … 111
11 … 110
11 … 101
ZS = V(IN-)
FS = V_REF +V(IN-
)
1LSB =
V _REF
4096
00 … 010
00 … 001
00 … 000
0123
(ZS)
Input Voltage (LSB)
FS
FS-3/2 LSB
Output Code
01 … 111
01 … 110
00 … 011
00 … 001
00 … 000
11 … 111
11 … 110
11 … 101
ZS = V(IN-)
+ FS = ½V_REF +V(IN-)
- FS = -½V_REF +V(IN-)
1LSB =
V_REF
4096
10 … 001
10 … 000
-FS
ZS
Input Voltage (LSB)
+FS
+FS-3/2 LSB
Figure 14: Unipolar Transfer Function
Figure 15: Bipolar Transfer Function
2.5. Power Dissipation
ZADCS146 and ZADCS147 offer three different ways to save operating current between conversions. Two
different software controlled power down modes can be activated to automatically shut-down the device after
completion of a conversion. They differ in the amount of circuitry that is powered down.
Software Power Down
Full Power Down Mode shuts down the entire analog part of the IC, reducing the static IDD of the device to
less than 0.5µA if no external clock is provided at SCLK. Fast Power Down mode is only useful with
ZADCS146 devices if the internal voltage reference is used. During Fast Power-Down the bandgap and the
VREFADJ output buffer are kept alive while all other internal analog circuitry is shut down. The benefit of Fast
Power Down mode is a shorter turn on time of the reference compared to Full Power-Down Mode. This is
basically due to the fact that the low pass which is formed at the VREFADJ output by the internal 20kΩ
resistor and the external buffer capacitor of 47nF is not discharged in Fast Power-Down Mode. The settling
time of the low pass at VREFADJ is about 9ms to reach 12 bit accuracy. The Fast Power Down mode omits
this settling and reduces the turn on time to about 200µs. To wake up the IC out of either software power
down mode, it is sufficient to send a Start Bit while nCS is LOW. Since micro controllers can commonly
transfer full bytes per transaction only, a dummy conversion is usually carried out to wake the device.
In all application cases where an external reference voltage is supplied (ZADCS147 and ZADCS146 with
VREFADJ tied to VDD) there is no turn on time to be considered. The first conversion is already valid. Fast
Power-Down and Full Power-Down Mode do not show any difference in this configuration.
Data Sheet
October 12, 2011
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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