ZADCS146_11 Datasheet, PDF (16/26 Pages) List of Unclassifed Manufacturers – 12-Bit, 200ksps, ADC Family

ZADCS146/147
12-Bit, 200ksps, ADC Family
In bipolar mode, IN₊ can range from (IN_– - Vref/2) to
(IN_–+Vref/2) keeping the converter out of code
saturation. For instance, if IN_– is set to a constant DC
voltage of Vref/2, then IN₊ can vary from 0V to V_REF to
cover the entire code range. Lower or higher voltages of
CH0
IN₊ keep the output code at the minimum or maximum
code value.
CH1
CH2
Figure 5 shows the input voltage ranges in bipolar mode
when IN_– is set to a constant DC voltage.
CH3
CH4
CH5
As explained before, ZADCS146 /ZADCS147 can also
CH6
be used to convert fully differential input signals that
CH7
change around a common mode input voltage.
The bipolar mode is best used for such purposes since
it allows the input signals to be positive or negative in
relation to each other.
Shown configuration
A2 … A0 = 0x000
IN+
Converter
IN-
The common mode level of a differential input signal is
calculated V_CM = (V(IN₊)+ V(IN_–)) / 2. To avoid code
clipping or over steering of the converter, the common
mode level can change from ¼ V_REF … ¾ V_REF. Within
this range the peak to peak amplitude of the differential
input signal can be ± V_REF/2.
The average input current on the analog inputs depends
on the conversion rate. The signal source must be
capable of charging the internal sampling capacitors
(typically 16pF on each input of the converter: IN₊ and
IN_–) within the acquisition time t_ACQ to the required
accuracy. The equivalent input circuit in sampling mode
is shown in Figure 7.
COM
See Table 3 & Table 4
for Coding Schemes
SGL/DIF = HIGH
Figure 6: Block diagram of input multiplexer
The following equation provides a rough hand calculation for a source impedance R_S that is required to settle
out a DC input signal referenced to AGND with 8 bit accuracy in a given acquisition time
R_S

t _ACQ
9  C_IN
 R_SW
For example, if f_SCLK = 3.2MHz, the acquisition
time is t_ACQ = 781.25ns. Thus the output
CH0
impedance of the signal source R_S must be less
than
CH1
CH2
CH3
R_S

781.25ns
9  20pF

3kΩ
 1.34kΩ
CH4
CH5
CH6
CH7
C _HOLD+
IN_{+ CIN}
4pF _16pF
AGND
C _HOLD-
R _SW
3kΩ
R _SW
V _DC
If the output impedance of the source is higher ^COM
than the calculated maximum R_S the acquisition
time must be extended by reducing f_SCLK to
Channel
Multiplexer
IN_{- CIN}
4pF _16pF
3kΩ
ensure 8 bit accuracy. Another option is to add a
AGND
capacitor of > 20nF to the individual input.
Although this limits the bandwidth of the input _{Figure 7: Equivalent input circuit during sampling}
signal because an RC low pass filter is build
together with the source impedance, it may be useful for certain applications.
Data Sheet
October 12, 2011
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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