ZADCS146_11 Datasheet, PDF (10/26 Pages) List of Unclassifed Manufacturers – 12-Bit, 200ksps, ADC Family

ZADCS146/147
12-Bit, 200ksps, ADC Family
1.3.2. Specific Parameters of ZADCS146 versions
(VDD = +2.7V to + 5.25V; f_SCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); _OP = _OPmin … _OPmax)
Parameter
Symbol Conditions
Min
Internal Reference at VREF
VREF Output Voltage
VREF Short-Circuit Current
T_A = + 25°C
2.480
VREF Temperature Coefficient
Load Regulation
0 to 0.2mA output load
Capacitive Bypass at VREF
4.7
Capacitive Bypass at REFADJ
0.047
REFADJ Adjustment Range
External Reference at VREF (internal buffer disabled by V(REFADJ) = VDD)
VREF Input Voltage Range
1.0
VREF Input Current
VREF = 2.5V
VREF Input Resistance
11.5
Shutdown VREF Input Current
Typ
2.500
± 30
0.35
 1.5
180
14
Max Unit
2.520
30
± 50
V
mA
ppm/°C
mV
µF
µF
%
VDD +
50mV
V
215 µA
k
0.1 µA
REFADJ Buffer Disable Threshold
VDD-
0.5
V
External Reference at VREF_ADJ
Reference Buffer Gain
VREF_ADJ Input Current
Full Power Down
VREFADJ Input Current
Full Power-Down mode
2.00
±80 µA
0.1 µA
Power Requirements
Positive Supply Voltage
Positive Supply Current
ZADCS146
ZADCS147
Positive Supply Current
ZADCS146
ZADCS147
VDD
IDD
IDD
2.7
Operating Mode ext. VREF
VDD=3.6V ^{Operating Mode int. VREF}
Fast Power-Down
Full Power-Down
Operating Mode ext. VREF
VDD=5.2V ^{Operating Mode int. VREF}
Fast Power-Down
Full Power-Down
5.25 V
0.85 1.0 mA
1.3 1.4 mA
250
300
µA
0.5 4.0
1.00 1.3 mA
1.40 1.6 mA
250
300
µA
0.5 4.0
Data Sheet
October 12, 2011
© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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