DS_FT2232D Datasheet, PDF (8/61 Pages) List of Unclassifed Manufacturers – Future Technology Devices International Ltd

Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
3.1 Pin Out Description
This section describes the operation of the FT2232D pins. Common pins are defined in the first section,
and then the I/O pins are defined by chip mode.
Note: The convention used throughout this document for active low signals is the signal name followed
by#
3.2 Common Pins
The operation of the following FT2232D pins do not change regardless of the configured mode:-
Pin No. Name Type
Description
7
USBDP
I/O USB Data Signal Plus ( Requires 1.5K pull-up to 3V3OUT or RSTOUT# )
8
USBDM
I/O USB Data Signal Minus
Table 3.1.1 USB Interface Group
Pin No. Name
Type
Description
48
EECS
I/O
EEPROM – Chip Select. Tri-State during device reset. **Note 1
1
EESK
OUTPUT Clock signal to EEPROM. Tri-State during device reset, else drives out.
**Note 1
EEDATA
I/O
EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to
2
Data-Out of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the
EEPROM to VCC via a 10K resistor for correct operation. Tri-State during
device reset. **Note 1
Table 3.2.2 EEPROM Interface Group
Pin No. Name
Type
Description
4
RESET# INPUT Can be used by an external device to reset the FT2232D. If not
required, tie to VCC. **Note 1
5
RSTOUT# OUTPUT Output of the internal Reset Generator. Drives low for 5.6 ms after VCC
> 3.5V and the internal clock starts up, then clamps it‟s output to the
3.3V output of the internal regulator. Taking RESET# low will also force
RSTOUT# to drive low. RSTOUT# is NOT affected by a USB Bus Reset.
47
TEST
INPUT Puts device into I.C. test mode – must be tied to GND for normal
operation.
41
PWREN# OUTPUT Goes Low after the device is configured via USB, then high during USB
suspend. Can be used to control power to external logic using a P-
Channel Logic Level MOSFET switch. Enable the Interface Pull-Down
Option in EEPROM when using the PWREN# pin in this way.
43
XTIN
INPUT Input to 6MHz Crystal Oscillator Cell. This pin can also be driven by an
external 6MHz clock if required. Note: Switching threshold of this pin is
VCC/2, so if driving from an external source, the source must be
driving at 5V CMOS level or a.c. coupled to centre around VCC/2.
44
XTOUT OUTPUT Output from 6MHz Crystal Oscillator Cell. XTOUT stops oscillating
during USB suspend, so take care if using this signal to clock external
logic.
Table 3.3.3 Miscellaneous Signal Group
**Note 1 - During device reset, these pins are tri-state but pulled up to VCC via internal 200K resistors.
Copyright © 2010 Future Technology Devices International Limited
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