DS_FT2232D Datasheet, PDF(44/61 Page) List of Unclassifed Manufacturers – Future Technology Devices International Ltd

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DS_FT2232D Datasheet, PDF (44/61 Pages) List of Unclassifed Manufacturers – Future Technology Devices International Ltd

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Document No.: FT_000173

FT2232D DUAL USB TO SERIAL UART/FIFO IC Datasheet

Version 2.05

Clearance No.: FTDI# 127

8.6 MCU Host Bus Emulation Mode Signal Descriptions and Interface

Configuration

MCU host bus emulation mode uses both of the FT2232Dâs A and B channel interfaces to make the chip

emulate a standard 8048 / 8051 MCU host bus. This allows peripheral devices for these MCU families to

be directly connected to USB via the FT2232D.

The lower 8 bits (AD7 to AD0) is a multiplexed Address / Data bus. A8 to A15 provide upper (extended)

addresses.

There are 4 basic operations:-

1) Read (does not change A15 to A8)

2) Read Extended (changes A15 to A8)

3) Write (does not change A15 to A8)

4) Write Extended (changes A15 to A8)

Enabling

MCU Host Bus Emulation mode is enabled using Set Bit Bang Mode driver command. A hex value of 8 will

enable it, and a hex value of 0 will reset the device. See application note AN2232-02, âBit Mode

Functions for the FT2232Dâ for more details and examples.

The MCU Host Bus Emulation Mode command set is fully described in application note AN_108,

âCommand Processor For MPSSE and MCU Host Bus Emulation Modesâ.

When MCU Host Bus Emulation mode is enabled the IO signal lines on both channels work together and

the pins are configured as follows :-

Pin#

Signal

Type

Description

AD0

I/O

Address / Data Bus Bit 0 **Note 28

AD1

I/O

Address / Data Bus Bit 1 **Note 28

AD2

I/O

Address / Data Bus Bit 2 **Note 28

AD3

I/O

Address / Data Bus Bit 3 **Note 28

AD4

I/O

Address / Data Bus Bit 4 **Note 28

AD5

I/O

Address / Data Bus Bit 5 **Note 28

AD6

I/O

Address / Data Bus Bit 6 **Note 28

AD7

I/O

Address / Data Bus Bit 7 **Note 28

I/O0

I/O

MPSSE mode instructions to set / clear or read the

high byte of data can be used with this pin. **Note

28, **Note 29

I/O1

I/O

MPSSE mode instructions to set / clear or read the

high byte of data can be used with this pin. In

addition this pin has instructions which will make

the controller wait until it is high, or wait until it is

low. This can be used to connect to an IRQ pin of a

peripheral chip. The FT2232D will wait for the

interrupt, and then read the device, and pass the

answer back to the host PC. I/O1 must be held in

input mode if this option is used. **Note 28,

**Note 29

IORDY

INPUT

Extends the time taken to perform a Read or Write

operation if pulled low. Pull up to Vcc if not being

used.

OSC

OUTPUT

Shows the clock signal that the circuit is using.

OUTPUT

Extended Address Bus Bit 8

OUTPUT

Extended Address Bus Bit 9

A10

OUTPUT

Extended Address Bus Bit 10

A11

OUTPUT

Extended Address Bus Bit 12

A12

OUTPUT

Extended Address Bus Bit 13

A13

OUTPUT

Extended Address Bus Bit 14

A14

OUTPUT

Extended Address Bus Bit 15

A15

OUTPUT

Extended Address Bus Bit 16

CS#

OUTPUT

Negative pulse to select device during Read or

Write.

ALE

OUTPUT

Positive pulse to latch the address.

RD#

OUTPUT

Negative Read Output.

WR#

OUTPUT

Negative Write Output. (Data is setup before WR#

goes low, and is held after WR# goes high)

Table 8.10 MCU Host Bus Emulation Mode IO Signal Lines Configuration

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