DS_FT2232D Datasheet, PDF (40/61 Pages) List of Unclassifed Manufacturers – Future Technology Devices International Ltd

Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
Figure 8.8 illustrates a typical interface between one of the channels of the FT2232D, configured in 245-
style FIFO interface mode, and a Microcontroller (MCU). Either channel A or B, or both can be configured
in this mode.
This examples uses two IO Ports of the MCU, one port (8 bits) to transfer data to one of the and the
other port (4 / 5 bits) to monitor the TXE# and RXF# status bits and generate the RD# and WR strobes
to the FT2232D as required. Optionally, SI / WU can be connected to another IO pin if either of the
functions of this pin are required. If the SI / WU function is not required, tie this pin to VCCIO. If the MCU
is handling power management functions, then PWREN# should also be connected to an IO pin of the
MCU.
The 8 data bits on IO Port 1 can be shared with other peripherals when the MCU is not accessing the
FT2232D
8.4 Enhanced Asynchronous and Synchronous Bit-Bang Modes - Signal
Description and Interface Configuration
Bit-bang mode is a special FT2232D device mode that changes the 8 IO lines on either (or both) channels
into an 8 bit bi-directional data bus. The are two types of Bit-bang mode for the FT2232D - Enhanced
Asynchronous Bit-Bang Mode, which is virtually the same as FTDI BM chip-style Bit-Bang mode, with the
addition of Read and Write strobes; and Synchronous Bit-Bang mode, where data is only read from the
device when the device is written to. Bit-Bang mode is enabled by driver command. When either Channel
A or Channel B (or both) have Enhanced Asynchronous Bit-Bang mode, or Synchronous Bit-Bang mode
enabled the IO signal lines are configured as follows :-
Pin#
Signal
Type
Description
Channel A Channel B
24
40
D0
I/O
23
39
D1
I/O
22
38
D2
I/O
21
37
D3
I/O
20
36
D4
I/O
19
35
D5
I/O
17
33
D6
I/O
16
32
D7
I/O
Table 8.6 Bit-Bang Data Bus Group **Note 24
Bit-Bang Data Bus Bit 0
Bit-Bang Data Bus Bit 1
Bit-Bang Data Bus Bit 2
Bit-Bang Data Bus Bit 3
Bit-Bang Data Bus Bit 4
Bit-Bang Data Bus Bit 5
Bit-Bang Data Bus Bit 6
Bit-Bang Data Bus Bit 7
**Note 24: In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be
programmed to gently pull low during USB suspend (PWREN# = “1” ) by setting this option in the
EEPROM.
Pin#
Signal Type
Description
Channel A
15
13
12
11
10
Channel B
30
29
28
27
26
WR#
RD#
WR#
RD#
SI/WU
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
Table 8.7 Bit-Bang Control Interface Group
**Note 25
**Note 25
**Note 26
**Note 26
The Send Immediate / WakeUp signal combines two
functions on a single pin. If USB is in suspend mode
(PWREN# = 1) and remote wakeup is enabled in the
EEPROM , strobing this pin low will cause the device to
request a resume on the USB Bus. Normally, this can be
used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is
strobed low any data in the device TX buffer will be sent
out over USB on the next Bulk-IN request from the
drivers regardless of the pending packet size. This can
be used to optimise USB transfer speed for some
applications. Tie this pin to VCCIO if not used
Copyright © 2010 Future Technology Devices International Limited
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