DS_FT2232D Datasheet, PDF (45/61 Pages) List of Unclassifed Manufacturers – Future Technology Devices International Ltd

Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
**Note 28: In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to
gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.
**Note 29: These instructions are fully described in the application note AN2232L-01 - “Command Processor For
MPSSE and MCU Host Bus Emulation Modes”.
Figure 8.10 MCU Host Bus Emulation Mode Signal Timing - Write Cycle
Time
Description
t1
High address byte is placed on the bus if the extended write is used.
t2
Low address byte is put out.
t3
1 clock period for address is set up.
t4
ALE goes high to enable latch. This will extend to 2 clocks wide if IORDY is
low.
t5
ALE goes low to latch address and CS# is set active low.
t6
Data driven onto the bus.
t7
1 clock period for data setup.
t8
WR# is driven active low. This will extend to 6 clocks wide if IORDY is low.
t9
WR# is driven inactive high.
t10
CS# is driven inactive, 1/2 a clock period after WR# goes inactive
t11
Data is held until this point, and may now change
Table 8.11 MCU Host Bus Emulation Mode Signal Timing - Write Cycle
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