DS_FT2232D Datasheet, PDF (46/61 Pages) List of Unclassifed Manufacturers – Future Technology Devices International Ltd

Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
Figure 8.11 MCU Host Bus Emulation Mode Signal Timing - Read Cycle
Time
Description
t1
High address byte is placed on the bus if the extended read is used -
otherwise t1 will not occur.
t2
Low address byte is put out.
t3
1 clock period for address set up.
t4
ALE goes high to enable address latch. This will extend to 2 clocks wide if
IORDY is low.
t5
ALE goes low to latch address, and CS# is set active low. This will extend to 3
clocks if IORDY is sampled low. CS# will always drop 1 clock after ALE has
gone high no matter the state of IORDY.
t6
Data is set as input (Hi-Z), and RD# is driven active low.
t7
1 clock period for data setup. This will extend to 5 clocks wide if IORDY# is
sampled low.
t8
RD# is driven inactive high.
t9
CS# is driven inactive 1/2 a clock period after RD# goes inactive, and the
data bus is set back to output.
Table 8.12 MCU Host Bus Emulation Mode Signal Timing - Read Cycle
Figure 8.12 MCU Host Bus Emulation Mode Signal Timing - Clock (OSC) Signal
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