DS_FT2232D Datasheet, PDF(60/61 Page) List of Unclassifed Manufacturers – Future Technology Devices International Ltd

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DS_FT2232D Datasheet, PDF (60/61 Pages) List of Unclassifed Manufacturers – Future Technology Devices International Ltd

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Document No.: FT_000173

FT2232D DUAL USB TO SERIAL UART/FIFO IC Datasheet

Version 2.05

Clearance No.: FTDI# 127

List of Tables

Table 1.1 Part Numbers ................................................................................................................. 2

Table 3.1.1 USB Interface Group .................................................................................................... 8

Table 3.2.2 EEPROM Interface Group............................................................................................... 8

Table 3.3.3 Miscellaneous Signal Group ........................................................................................... 8

Table 3.4.4 Power and Ground Group .............................................................................................. 9

Table 3.5.5 Pin Definition by Chip Mode (Channel A) ....................................................................... 10

Table 3.6.6 Pin Definition by Chip Mode (Channel B) ....................................................................... 11

Table 3.7.7 IO Mode Command Hex Values ..................................................................................... 12

Table 5.1 Absolute Maximum Ratings ........................................................................................... 16

Table 5.2 Operating Voltage and Current ....................................................................................... 17

Table 5.3 IO Pin Characteristics (VCCIO = 5.0V, Standard Drive Level) **Note 12 .............................. 17

Table 5.4 IO Pin Characteristics (VCCIO = 3.0V â 3.6V, Standard Drive Level) **Note 12.................... 17

Table 5.5 IO Pin Characteristics (VCCIO = 5.0V, Standard Drive Level) **Note 12 and 13 .................. 18

Table 5.6 IO Pin Characteristics (VCCIO = 3.0V -3.6V, Standard Drive Level) **Note 12 and 13 .......... 18

Table 5.7 XTIN / XTOUT Pin Characteristics ................................................................................... 18

Table 5.8 RESET# and TEST EECS, EESK, EEDATA Pin Characteristics **Note 14 .............................. 19

Table 5.9 RSTOUT# Pin Characteristics......................................................................................... 19

Table 5.10 USB I/O Pin (USBDP, USBDM) Characteristics **Note 15 ................................................ 19

Table 5.11 ESD Tolerance ............................................................................................................ 20

Table 8.1 232 UART mode the IO signal lines Description................................................................ 31

Table 8.2 FIFO Data Bus Group **Note 17 ..................................................................................... 37

Table 8.3 FIFO Control Interface Group ......................................................................................... 37

Table 8.4 Read Cycle................................................................................................................... 38

Table 8.5 Write Cycle .................................................................................................................. 39

Table 8.6 Bit-Bang Data Bus Group **Note 24 ............................................................................... 40

Table 8.7 Bit-Bang Control Interface Group .................................................................................... 40

Table 8.8 Synchronous Bit Bang Mode Signal Timing ....................................................................... 42

Table 8.9 MPSSE Mode Configuration ............................................................................................ 43

Table 8.10 MCU Host Bus Emulation Mode IO Signal Lines Configuration ........................................... 44

Table 8.11 MCU Host Bus Emulation Mode Signal Timing - Write Cycle .............................................. 45

Table 8.12 MCU Host Bus Emulation Mode Signal Timing - Read Cycle............................................... 46

Table 8.13 MCU Host Bus Emulation Mode Signal Timing - Clock (OSC) Signal.................................... 47

Table 8.14 Fast Opto-Isolated Serial Interface Mode IO Signal Lines Configuration.............................. 48

Table 8.15 Fast Opto-Isolated Serial Signal Timing Diagram............................................................. 49

Table 8.16 FIFO Data Bus Group **Note 20 ................................................................................... 52

Table 8.17 FIFO Control Interface Group........................................................................................ 52

Table 8.18 Chip Select bit and Address bit truth table ..................................................................... 52

Table 8.19 Status Data bits .......................................................................................................... 52

Table 8.20 CPU FIFO Interface Mode - Signal Timing ....................................................................... 53

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