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DS_FT2232D Datasheet, PDF (52/61 Pages) List of Unclassifed Manufacturers – Future Technology Devices International Ltd
Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
8.8 CPU FIFO Interface Mode Signal Descriptions and Configuration
Examples
CPU-style FIFO interface mode is designed to allow a CPU to interface to USB via the FT2232D. This mode
is enabled in the external EEPROM. The interface is achieved using a chip select bit (CS#) and address bit
(A0).
When either Channel A or Channel B are in CPU FIFO Interface mode the IO signal lines are configured as
follows:-
Pin#
Signal
Type
Description
Channel A Channel B
24
40
D0
I/O
23
39
D1
I/O
22
38
D2
I/O
21
37
D3
I/O
20
36
D4
I/O
19
35
D5
I/O
17
33
D6
I/O
16
32
D7
I/O
Table 8.16 FIFO Data Bus Group **Note 20
FIFO Data Bus Bit 0
FIFO Data Bus Bit 1
FIFO Data Bus Bit 2
FIFO Data Bus Bit 3
FIFO Data Bus Bit 4
FIFO Data Bus Bit 5
FIFO Data Bus Bit 6
FIFO Data Bus Bit 7
Pin#
Signal Type
Description
Channel A Channel B
15
30
CS# INPUT
13
29
A0
INPUT
12
28
RD# INPUT
11
27
WR# INPUT
Table 8.17 FIFO Control Interface Group
Chip Select Bit ** Note 20
Address Bit ** Note 20
Negative read input ** Note 20
Negative write input ** Note 20
**Note 20: In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be
programmed to gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the
EEPROM
CS#
A0
1
X
0
0
0
1
Table 8.18 Chip Select bit and Address bit truth table
RD#
X
Read Data Pipe
Read Status
WR#
X
Write Data Pipe
Send Immediate **Note 21
Key: X = Not Used; 1 = Signal off; 0 = Signal off
**Note 21: Has to be clocked by USB clock
Data Bit
bit 0
bit 1
bit 2
bit 3
bit 4 **Note 22
bit 5 **Note 22
bit 6 **Note 22
bit 7 **Note 22
Table 8.19 Status Data bits
Data
1
1
1
1
X
X
X
X
Key: X = Not Used; 1 = Signal off; 0 = Signal off
**Note 22: bits 4 to 7 will have arbitrary values when the status is read.
Status
Data Available (=RXF)
Space Available (=TXE)
Suspend
Configured
X
X
X
X
Copyright © 2010 Future Technology Devices International Limited
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