SI8513-C-IS Datasheet, PDF (13/37 Pages) List of Unclassifed Manufacturers – Si85XX UNIDIRECTIONAL AC CURRENT SENSORS

Si85xx
3. Application Information
3.1. Board Layout
The Si85xx is connected in the series path of the current
to be measured. The Si85xx must be located as far as
possible from transformer and other magnetic field
sources. Like other analog components, the Si85xx
should be powered from a low-noise dc source and,
preferably, to a low-noise analog ground plane.
Recommended bypass capacitors are 1 µF in parallel
with a 0.1 µF, positioned as close to the Si85xx as
possible. When using the Si850x (single output
versions), all three ground pins MUST be connected to
the same ground point, and both VDD1 and VDD2 pins
MUST be tied to the VDD system power supply.
3.2. Layout Requirements
The Si85xx requires special layout techniques to ensure
proper operation (see Figures 9 and 10). Due to the
close proximity of the current-carrying slug and current
sensor silicon, magnetic coupling between the current-
carrying slug and the silicon can form a ground loop
causing the output voltage to be 0 V even though
current is flowing through the slug. To eliminate any
such coupling issues, a red fly-wire VDD trace (see
Figures 9 and 10) should be implemented in the layout.
For the SOIC package, the red fly-wire trace should be
approximately 3.5 mm from the center edge of the
package intersecting approximately in the center of the
package (see Figure 9). For the QFN package, the red
fly-wire should be approximately in the center of the
package (see Figure 10). Standard wire thicknesses for
10 mA current-carrying capabilities should be used.
Moreover, note that the fly-wire trace should be
completely under the ground plane since this will also
reduce coupling.
Regarding isolation voltage requirements, the trace
does not need to follow the lead frame and bonding
traces exactly, as long as the net magnetic flux is close
to zero. The goal here is to keep the magnetic coupling
small and, at the same time, keep the isolation distance
large. Moreover, to ensure that the layout meets the
design’s required creepage and clearance
requirements, the VDD trace should be placed on one
of the inner layers or even the back side of the board.
For example, one can lay out the return VDD trace on
the other side of the PCB so the PCB itself can help to
provide high isolation voltage.
VDD Pin
Mode Pin
(Non-Ping-Pong)
Ground
Plane Edge
Top View
VDD Fly Wire
3.5 mm
Bonding Wire
Ground
Plane Edge
Current
Carrying Slug
Current
Sensor Die
Gnd Pin
Bypass Capacitor
5 V VDD Trace
SOIC Package
Figure 9. SOIC Layout Requirements
Ground Plane Edge
VDD Pin
Mode Pin
(Non-Ping-Pong)
Top View
Ground
Plane Edge
Current
Carrying Slug
Bonding
Wires
2 mm
VDD
Fly Wire
Current
Sensor Die
Bypass Capacitor
5V VDD Trace
Gnd Pin
QFN Package
Figure 10. QFN Layout Requirements
Preliminary Rev. 0.4
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