QL82SD Datasheet, PDF (42/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
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E
QD
R
E
DQ
PAD
R
E
DQ
R
Figure 51: QuickSD I/O Cell
The bi-directional I/O pin options can be programmed for input, output, or bi-directional
operation. Each bi-directional I/O pin is associated with an I/O cell which features an
input/feedback register, an input buffer, output/feedback register, three-state output buffer,
an output enable register, and two 2-to-1 multiplexers.
For input functions, I/O pins can provide combinatorial registered data or both options
simultaneously to the logic array. For combinatorial input operation, data is routed from I/O
pins through the input buffer to the array logic. For registered input operation, I/O pins drive
the D input of input cell registers, allowing data to be captured with fast set-up times without
consuming internal logic cell resources.
For output functions, I/O pins can receive combinatorial or registered data from the logic
array. For combinatorial output operation, data is routed from the logic array through a
multiplexer to the I/O pin. For registered output operation, the array logic drives the D input
of the output cell register which in turn drives the I/O pin through a multiplexer. The
multiplexer allows either a combinatorial or a registered signal to be driven to the I/O pin.
The three-state output buffer controls the flow of data from the array logic to the I/O pin and
allows the I/O pin to act as an input and/or output. The buffer's output enable can be
individually controlled by a logic cell array or any pin (through the regular routing resources),
or bank-controlled through one of the global networks.
The signal can also be either combinatorial or registered. This is identical to that of the flow
for the output cell. For combinatorial control operation, data is routed from the logic array
through a multiplexer to the three-state control. For registered control operation, the array
logic drives the D input of the OE cell register which in turn drives the three-state control
through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to
be driven to the three-state control.
For output functions, I/O pins can be individually configured for active HIGH, active LOW,
or open-drain inverting operation. In the active HIGH and active LOW modes, the pins of
all devices are fully 3.3 V compliant.
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Preliminary
© 2002 QuickLogic Corporation