QL82SD Datasheet, PDF (3/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

General Description
QL82SD Device Data Sheet Rev C
LVDS SERDES Transmitter and Receiver
A QuickSD LVDS SERDES device in serializer mode takes a parallel data bus and a separate
clock and converts them into a serial data stream. In deserializer mode, it takes a serial data
stream and converts it to a configurable bit wide parallel data bus and separate clock. The
reduced number of I/O board traces and cable connectors saves on cost and significantly
simplifies design. Skew and timing issues are significantly reduced and performance is
enhanced. Figure 2 and Figure 3 illustrate the block diagrams of the QuickSD device
transmitter and receiver.
Parallel to Serial
.
.
txd [9:0]
.
.
/Enable
RL = 27 ^Ω - 100 ^Ω
Vo -
Vo +
IL = 8-12 mA
300k
Do +
Do -
300k
Figure 2: LVDS SERDES Transmitter Block Diagram
300k W
Din +
VCM = 0.2 V - 2.2 V
Din -
300k W
Serial to Parallel
FPGA
TTL_Din
.
.
. ^{rxd [9:0]}
.
Figure 3: LVDS SERDES Receiver Block Diagram
© 2002 QuickLogic Corporation
Preliminary
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