QL82SD Datasheet, PDF (26/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
Table 25: Standard Input Delays
Symbol
Parameter
Standard
Input Delays
t_{SID (LVTTL)}
t_{SID (LVCMOS2)}
t_{SID (GTL+)}
t_{SID (SSTL3)}
t_{SID (SSTL2)}
To get the total input delay and this delay to tISU
LVTTL input delay: Low Voltage TTL for 3.3 V applications
LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and
lower applications
GTL+ input delay: Gunning Transceiver Logic
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V
SSTL2 input delay: Stub Series Terminated Logic for 2.5V
Propagation
delay (ns)
0.34
0.42
0.68
0.55
0.607
R
CLK
D
tISU
tIH
Q
tICLK
tIRST
E
tIESU
tIEH
Figure 37: Input Register Timing
PAD
OUTPUT
REGISTER
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26
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Figure 38: Output Register Cell
Preliminary
© 2002 QuickLogic Corporation