QL82SD Datasheet, PDF (29/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
RAM Cell Read Timing
Table 28: RAM Cell Synchronous and Asynchronous Read Timing
Symbol
Parameter
RAM Cell Synchronous Read Timing
t_SRA
RA setup time to RCLK: the amount of time the READ ADDRESS
must be stable before the active edge of the READ CLOCK
t_HRA
RA hold time to RCLK: the amount of time the READ ADDRESS
must be stable after the active edge of the READ CLOCK
t_SRE
RE setup time to WCLK: the amount of time the READ ENABLE
must be stable before the active edge of the READ CLOCK
t_HRE
RE hold time to WCLK: the amount of time the READ ENABLE
must be stable after the active edge of the READ CLOCK
t_RCRD
RCLK to RD: the amount of time between the active READ CLOCK
edge and the time when the data is available at RD
RAM Cell Asynchronous Read Timing
r_PDRD
RA to RD: amount of time between when the READ ADDRESS is
input and when the DATA is output
Propagation
delay (ns)
0.686
0
0.243
0
4.38
2.06
RCLK
RA
RE
RD
TSRA
THRA
TSRE
THRE
OLD data
NEW data
TRCRD
RPDRD
Figure 42: RAM Cell Synchronous and Asynchronous Read Timing
© 2002 QuickLogic Corporation
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