QL82SD Datasheet, PDF (22/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
Super Logic (Flip-Flop and Combinational Circuit) AC Characteristics at
VCC = 2.5 V, TA = 25^o C (K = 1)
Symbol
set
q
d
clk
reset
Figure 28: Super Logic Cell Flip-Flop Structure
Table 21: Logic Cells
Propagation delay (ns)
Parameter
Condition
Fanout = 1
t_PD
t_SU
t_H
t_CLK
t_CWHI
t_CWLO
t_SET
t_RESET
t_SW
t_RW
Combinational Delay ^a
Setup Time ^b
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
0.257
0.22
0
0.255
0.46
0.46
0.18
0.09
0.30
0.30
a. Stated timing for worst case Propagation Delay over process variation at VCC = 2.5 V and
TA = 25 °C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature
settings as specified in the operating range.
b. These limits are derived from a representative selection of the slowest paths through the logic cell
including typical net delays. Worst case delay values for specific paths should be determined from
timing analysis of your particular design.
input
output
tPD
Figure 29: Combinational Delay for Logic Cell
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Preliminary
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