QL82SD Datasheet, PDF (2/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
Programmable I/O
• Up to 252 Programmable I/O pins
• High performance Enhanced I/O (EIO): Less than 3 ns Tco
• Programmable Slew Rate Control
• Programmable I/O Standards
• LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3, LVDS, LVPECL
• Four Independent I/O Banks
• Three Register Configuration: Input, Output, OE
Embedded Computational Unit (ECU) Blocks
• Integrated multiply, add, and accumulate function
• 18 distributed MAC blocks
• 8 × 8 multiply (sign & unsigned)
• 16-bit carry add
Advanced Clock Network
• Nine Global Clock Networks consisting of:
• one dedicated
• eight programmable
• Eight I/O (high drive) networks: two I/Os per bank
• Ten Quad-Net Networks—five per quadrant
IO Block
IO Block
RAM Blocks
Embedded Computational Units (ECUs)
2016 Logic Cells
RAM Blocks
LVDS/SERDES IO Block
Figure 1: QL82SD Device Block Diagram
Customer Part #
QL82SD-PQ208
QL82SD-PT280
QL82SD-PS484
QL82SD-PB516
Table 1: QL82SD Device Table
SERDES LVDS SRAM Logic ECU
Data Clocks Blocks Cells Blocks
4
2
36 2016 18
8
2
36 2016 18
8
2
36 2016 18
8
2
36 2016 18
Programmable I/O
75
121
209
252
•
2
•
•
•
www.quicklogic.com
•
•
Preliminary
© 2002 QuickLogic Corporation