QL82SD Datasheet, PDF (20/60 Pages) List of Unclassifed Manufacturers – 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps

QL82SD Device Data Sheet Rev C
Pad_Clkx_p/n
t _{RXD [1] max}
t _{RXD [1] min}
t _{RXD [0] max}
t _{RXD [0] min}
SerialClock
(Internal)
t _SCD
Pad_Chx_p/n
t _RXDS
t _RXDH
t _RCP
t _SCP
Strobe
[bit3] [bit2] [bit1] [bit0] [bit7] [bit6] [bit5] [bit4]
Chx_rxd [7:0]
Note: ^t RXD [N-1] denotes
physical strobe positions
wrt Pad_ClkX_p/n while
Pad_ChX_p/n bit[n] refers
to logical bit positions
wrt ChX_rxd [7:0].
Chx_rxclk
t _DD
t _RXPD
Figure 26: Channel Link Mode Deserializer Receive (Using 8:1 Mode as Example)
Ch0_txd [0]
Pad_Ch0_p/n
t_ASD
ClkA_txclk
Pad_ClkA_p/n
t_ASC
Figure 27: 1:1 Mode Asynchronous Level Conversion Mode Deserializer Delays
SERDES Bit Error Rate
The following table indicates the SERDES bit error rate at TA = 25° C and
PLLVcc = 2.5 V unless otherwise specified.
Table 18: Serializer/Deserializer Bit Error Rate
Modes
10:1
Bit Error Rate
< 1 x 10^-12
8:1
< 1 x 10^-12
7:1
< 1 x 10^-12
4:1
< 1 x 10^-12
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Preliminary
© 2002 QuickLogic Corporation