NT5SV64M4AT Datasheet, PDF (36/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Operating, Standby, and Refresh Currents (T_A = 0 to +70°C, V_DD = 3.3V ±0.3V)
Parameter
Symbol
Test Condition
Speed
-7K
-75B
-8B
Operating Current
1 bank operation
I_{C C 1}
t_{R C} = t_RC(min), t _CK = min
Active-Precharge command cycling with-
130
120
115
out burst operation
Precharge Standby Current
in Power Down Mode
Precharge Standby Current
in Non-Power Down Mode
No Operating Current
(Active state: 4 bank)
I_CC2P
CKE ≤ V_IL(max), t_{C K} = min,
CS = V _{I H}(min)
I_CC2PS
CKE ≤ V_IL(max), t_{C K} = Infinity,
CS = V _{I H}(min)
I_CC2N
CKE ≥ V_{I H}(min), t_CK = min,
CS = V_IH (min)
I_CC2NS CKE ≥ V_{I H}(min), t_CK = Infinity,
I_CC3N
CKE ≥ V_{I H}(min), t_CK = min,
CS = V_IH (min)
I_CC3P CKE ≤ V_IL(max), t_{C K} = min,
2
2
2
2
2
2
30
30
20
8
8
8
60
60
45
6
6
6
t_CK = min,
Operating Current (Burst
Mode)
I_{C C 4}
Read/ Write command cycling,
Multiple banks active, gapless data, BL =
120
120
90
4
Auto (CBR) Refresh Current
I_{C C 5}
t_CK = min, t _{R C} = t_RC(min)
CBR command cycling
175
175
155
Self Refresh Current
I_{C C 6}
CKE ≤ 0.2V
SP
3
3
3
LP
1.2
1.2
1.2
Units Notes
mA 1, 2, 3
mA
1
mA
1
mA
1, 5
mA
1, 7
mA
1, 5
mA
1, 6
mA 1, 3, 4
mA
1
mA
1,8
mA
8
1. Currents given are valid for a single device. .
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t_CK and t_RC. Input sig-
nals are changed up to three times during t_RC(min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during t_CK(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
8. SP : Standard power ; LP : Lower power
REV 1.0
May, 2001
36
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