NT5SV64M4AT Datasheet, PDF (11/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock.
The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or
interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears
on the outputs is equal to the value of the CAS latency that is set in the Mode Register.
Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND ^{READ A}
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
t_CK2, DQs
CAS latency = 3
t_CK3, DQs
DOUT A ₀
DOUT A ₁
DOUT A₂
DOUT A ₃
DOUT A ₀
DOUT A₁
DOUT A ₂
DOUT A₃
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that
the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remain-
ing addresses are overridden by the new address with the full burst length. The data from the first Read Command continues to
appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the
interrupting Read Command appears.
Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND ^{READ A}
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
t_CK2, DQs
CAS latency = 3
t_CK3, DQs
DOUT A₀
DOUT B ₀
DOUT B₁
DOUT B ₂
DOUT B₃
DOUT A ₀
DOUT B ₀
DOUT B₁
DOUT B ₂
DOUT B₃
REV 1.0
May, 2001
11
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