NT5SV64M4AT Datasheet, PDF (29/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Command Truth Table (See note 1)
Function
CKE
Device State _{Previous Current} CS
Cycle
Cycle
Mode Register Set
Idle
H
X
L
Auto (CBR) Refresh
Idle
H
H
L
Entry Self Refresh
Idle
H
L
L
Exit Self Refresh
Idle (Self-
Refresh)
H
L
H
L
Single Bank Precharge
See Current
State Table
H
X
L
Precharge all Banks
See Current
State Table
H
X
L
Bank Activate
Idle
H
X
L
Write
Active
H
X
L
Write with Auto-Precharge Active
H
X
L
Read
Active
H
X
L
Read with Auto-Precharge Active
H
X
L
Reserved
H
X
L
No Operation
Any
H
X
L
Device Deselect
Any
H
X
H
Clock Suspend Mode Entry Active
H
L
X
Clock Suspend Mode Exit Active
L
H
X
Data Write/Output Enable Active
H
X
X
Data Mask/Output Disable Active
H
X
X
Power Down Mode Entry Idle/Active
H
H
L
L
Power Down Mode Exit
Any (Power
Down)
L
H
H
L
RAS CAS WE
L
L
L
L
L
H
L
L
H
X
X
X
H
H
H
L
H
L
L
H
L
L
H
H
H
L
L
H
L
L
H
L
H
H
L
H
H
H
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
X
X
X
H
H
H
DQM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
X
X
BA0,
BA1
A10
A12,
A11,
A9-A0
Notes
OP Code
X
X
X
X
X
X
X
X
X
BS
L
X
2
X
H
X
BS
Row Address
2
BS
L Column 2
BS
H Column 2
BS
L Column 2
BS
H Column 2
X
X
X
X
X
X
X
X
X
X
X
X
4
X
X
X
X
X
X
5
X
X
X
X
X
X
6, 7
X
X
X
6, 7
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the
Current State Truth Table.
2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1
selects bank 3.
3. Not applicable.
4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and
Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the
data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cy cles.
When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device
state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’t remain in
this mode longer than the Refresh period (t _REF) of the device. One clock delay is required for mode entry and exit.
7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
REV 1.0
May, 2001
29
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