NT5SV64M4AT Datasheet, PDF (17/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command
or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing accepts one extra
address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during
the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst opera-
tion is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write
Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as
normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed.
Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge can
also be implemented during Write commands.
A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or
Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read, Write, or
Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst oper-
ation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (t_RP) has
been satisfied.
When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal
precharge operation must satisfy t_RAS(min). If this interval does not satisfy t_RAS(min) then t_RCD must be extended.
Burst Read with Auto-Precharge
(Burst Length = 1, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND
READ A
Auto-Precharge
NOP
CAS latency = 2
t_CK2, DQs
CAS latency = 3
t_CK3, DQs
Begin Auto-precharge
NOP
NOP
t_{R P}‡
*
DOUT A ₀
t_RP‡
DOUT A₀
NOP
NOP
NOP
NOP
NOP
*
*^{Bank can be reactivated at completion of tRP.}
‡ t_RP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
REV 1.0
May, 2001
17
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