NT5SV64M4AT Datasheet, PDF (31/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Current State Truth Table (Part 1 of 3)(See note 1)
Current State
Idle
Row Active
Read
Write
Command
CS RAS CAS WE BA0,BA1 A12 - A0
Description
Action
LLLL
OP Code
Mode Register Set Set the Mode Register
LLLH
X
X
Auto or Self Refresh Start Auto or Self Refresh
L LHL
BS
X
Precharge
No Operation
L LHH
BS Row Address Bank Activate
Activate the specified bank and row
LHL L
BS
Column Write w/o Precharge ILLEGAL
LHL H
BS
Column Read w/o Precharge ILLEGAL
LHHH
X
X
No Operation
No Operation
HX XX
X
X
Device Deselect
No Operation or Power Down
LLLL
OP Code
Mode Register Set ILLEGAL
LLLH
X
X
Auto or Self Refresh ILLEGAL
L LHL
BS
X
Precharge
Precharge
L LHH
BS Row Address Bank Activate
ILLEGAL
LHL L
BS
Column Write
Start Write; Determine if Auto Precharge
LHL H
BS
Column Read
Start Read; Determine if Auto Precharge
LHHH
X
X
No Operation
No Operation
HX XX
X
X
Device Deselect
No Operation
LLLL
OP Code
Mode Register Set ILLEGAL
LLLH
X
X
Auto or Self Refresh ILLEGAL
L LHL
BS
X
Precharge
Terminate Burst; Start the Precharge
L LHH
BS Row Address Bank Activate
ILLEGAL
LHL L
BS
Column Write
Terminate Burst; Start the Write cycle
LHL H
BS
Column Read
Terminate Burst; Start a new Read cycle
LHHH
X
X
No Operation
Continue the Burst
HX XX
X
X
Device Deselect
Continue the Burst
LLLL
OP Code
Mode Register Set ILLEGAL
LLLH
X
X
Auto or Self Refresh ILLEGAL
L LHL
BS
X
Precharge
Terminate Burst; Start the Precharge
L LHH
BS Row Address Bank Activate
ILLEGAL
LHL L
BS
Column Write
Terminate Burst; Start a new Write cycle
LHL H
BS
Column Read
Terminate Burst; Start the Read cycle
LHHH
X
X
No Operation
Continue the Burst
HX XX
X
X
Device Deselect
Continue the Burst
Notes
2
2, 3
4
4
5
6
4
7, 8
7, 8
4
8, 9
8, 9
4
8, 9
8, 9
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is
being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank no t being refer-
enced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (t_RAS) must be satisfied.
7. The RAS to CAS Delay (t _RCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (t _RRD ) is not satisfied.
REV 1.0
May, 2001
31
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