NT5SV64M4AT Datasheet, PDF (14/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Burst Write Command
The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock.
The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the
first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining
data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has fin-
ished, any additional data supplied to the DQ pins will be ignored.
Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND ^NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQs
DIN A₀
DIN A ₁
: “H” or “L”
The first data element and the Write
are registered on the same clock edge.
DIN A ₂
DIN A ₃
Extra data is masked.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is inter-
rupted, the remaining addresses are overridden by the new address and data will be written into the device until the pro-
grammed burst length is satisfied.
Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND ^NOP
DQs
WRITE A
WRITE B
1 CK Interval
DIN A₀
DIN B ₀
NOP
DIN B ₁
NOP
DIN B ₂
NOP
DIN B ₃
NOP
NOP
NOP
REV 1.0
May, 2001
14
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