NT5SV64M4AT Datasheet, PDF (23/65 Pages) List of Unclassifed Manufacturers – 256Mb Synchronous DRAM

NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
Precharge Termination
The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command
is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to
appear on the data bus as a function of CAS Latency.
Burst Read Interrupted by Precharge
(Burst Length = 8, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND ^{READ Ax}0
NOP
CAS latency = 2
t_CK2, DQs
CAS latency = 3
t_CK3, DQs
NOP
NOP
Precharge A
NOP
t_RP‡
NOP
*
NOP
DOUT Ax₀ DOUT Ax₁ DOUT Ax₂ DOUT Ax₃
t_RP‡
*
DOUT Ax₀ DOUT Ax₁ DOUT Ax₂ D O U T A x₃
NOP
* ^{Bank A can be reactivated at completion of tRP.}
‡ t_{R P} is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
REV 1.0
May, 2001
23
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