TLC156 Datasheet, PDF (33/50 Pages) List of Unclassifed Manufacturers – EPROM/ROM-Based 8-Bit Microcontroller Series

TLC
TLC156
MOVAR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Move ACC to R
MOVAR R
0 ≤ R ≤ 63
ACC à R
None
Move data from the ACC register to register ‘R’.
1
MOVIA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Move Immediate to ACC
MOVIA I
0 ≤ I ≤ 255
I à ACC
None
The 8-bit immediate ‘I’is loaded into the ACC register. The don’t cares will assemble as 0s.
1
MOVR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Move R
MOVR R, d
0 ≤ R ≤ 63
d ∈ [0,1]
R à dest
Z
The contents of register ‘R’is moved to destination ‘d’. If ‘d’is 0, destination is the ACC
register. If ‘d’is 1, the destination is file register ‘R’. ‘d’is 1 is useful to test a file register since
status flag Z is affected.
1
NOP
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
No Operation
NOP
None
No operation
None
No operation.
1
OPTION
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Load OPTION Register
OPTION
None
ACC à OPTION
None
The content of the ACC register is loaded into the OPTION register.
1
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Return from Interrupt, Set ‘GIE’Bit
RETFIE
None
Top of Stack à PC
None
The program counter is loaded from the top of the stack (the return address). The ‘GIE’bit is
set to 1. This is a two-cycle instruction.
2
Rev0.95 Nov 20, 2003
P.2/TLC156