TLC156 Datasheet, PDF (29/50 Pages) List of Unclassifed Manufacturers – EPROM/ROM-Based 8-Bit Microcontroller Series

TLC
TLC156
BCR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Clear Bit in R
BCF R, b
0 ≤ R ≤ 63
0≤b≤7
0 à R<b>
None
Clear bit ‘b’in register ‘R’.
1
BSR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Set Bit in R
BSR R, b
0 ≤ R ≤ 63
0≤b≤7
1 à R<b>
None
Set bit ‘b’in register ‘R’.
1
BTRSC
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Test Bit in R, Skip if Clear
BTRSC R, b
0 ≤ R ≤ 63
0≤b≤7
Skip if R<b> = 0
None
If bit ‘b’in register ‘R’is 0 then the next instruction is skipped.
If bit ‘b’is 0 then next instruction fetched during the current instruction execution is discarded,
and a NOP is executed instead making this a 2-cycle instruction..
1(2)
BTRSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Test Bit in R, Skip if Set
BTRSS R, b
0 ≤ R ≤ 63
0≤b≤7
Skip if R<b> = 1
None
If bit ‘b’in register ‘R’is ‘1’then the next instruction is skipped.
If bit ‘b’is ‘1’, then the next instruction fetched during the current instruction execution, is
discarded and a NOP is executed instead, making this a 2-cycle instruction.
1(2)
CALL
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Subroutine Call
CALL I
0 ≤ I ≤ 1023
PC +1 à Top of Stack;
I à PC<9:0>
PCHBUF<2> à PC<10>
None
Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit immediate
address is loaded into PC bits <10:0>. CALL is a two-cycle instruction.
2
Rev0.95 Nov 20, 2003
P.2/TLC156