TLC156 Datasheet, PDF (32/50 Pages) List of Unclassifed Manufacturers – EPROM/ROM-Based 8-Bit Microcontroller Series

TLC
TLC156
INCRSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Increment R, Skip if 0
INCRSZ R, d
0 ≤ R ≤ 63
d ∈ [0,1]
R + 1 à dest, skip if result = 0
None
The contents of register ‘R’are incremented. If ‘d’is 0 the result is placed in the ACC register.
If ‘d’is the result is placed back in register ‘R’.
If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP is
executed instead making it a two-cycle instruction.
1(2)
INT
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
S/W Interrupt
INT
None
PC + 1 à Top of Stack,
002h à PC
None
Interrupt subroutine call. First, return address (PC+1) is pushed onto the stack. The address
002h is loaded into PC bits <10:0>.
2 for TLC155/157; 3 for TLC154/156
IORAR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
OR ACC with R
IORAR R, d
0 ≤ R ≤ 63
d ∈ [0,1]
ACC or R à dest
Z
Inclusive OR the ACC register with register ‘R’. If ‘d’is 0 the result is placed in the ACC
register. If ‘d’is 1 the result is placed back in register ‘R’.
1
IORIA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
OR Immediate with ACC
IORIA I
0 ≤ I ≤ 255
ACC or I à ACC
Z
The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
IOST
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Load IOST Register
IOST R
R = 5,6 or 7
ACC à IOST register R
None
IOST register ‘R’(R= 5,6 or7) is loaded with the contents of the ACC register.
1
Rev0.95 Nov 20, 2003
P.2/TLC156