TLC156 Datasheet, PDF (19/50 Pages) List of Unclassifed Manufacturers – EPROM/ROM-Based 8-Bit Microcontroller Series

TLC
TLC156
FIGURE 2.4: Block Diagram of The Timer0/WDT Prescaler
Instruction Cycle
(Fosc/4 or Fosc/2 or Fosc/8)
T0CKI
T0SE
0
MUX
1
T0CS
1
MUX
0
PSA
Sync
2 Cycles
TMR0
Register
8 _{Data Bus}
Set T0IF flag
on overflow
Watchdog
Timer
0
MUX
1
PSA
8-Bit
Prescaler
PS2:PS0
1
MUX
0
PSA
WDT Time-out
2.4 Interrupts
The TLC156 series has up to three sources of interrupt:
1. External interrupt INT pin.
2. TMR0 overflow interrupt.
3. Port B input change interrupt (pins IOB7:IOB0).
INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags.
A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all
interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register
regardless of the status of the GIE bit.
When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will
be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address 008h.
The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.
The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.
The flag bit (except PBIF bit) in INTFLAG register is set by interrupt event regardless of the status of its mask bit.
Reading the INTFLAG register will be the logic AND of INTFLAG and INTEN.
When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 002h.
2.4.1 External INT Interrupt
External interrupt on INT pin is rising or falling edge triggered selected by INTEDG (OPTION<6>).
When a valid edge appears on the INT pin the flag bit INTIF (INTFLAG<2>) is set. This interrupt can be disabled by
clearing INTIE bit (INTEN<2>).
The INT pin interrupt can wake-up the system from SLEEP condition, if bit INTIE was set before going to SLEEP. If
GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the
program will execute next PC after wake-up.
2.4.2 Timer0 Interrupt
An overflow (FFh à 00h) in the TMR0 register will set the flag bit T0IF (INTFLAG<0>). This interrupt can be
disabled by clearing T0IE bit (INTEN<0>).
Rev0.95 Nov 20, 2003
P.2/TLC156