TLC156 Datasheet, PDF (30/50 Pages) List of Unclassifed Manufacturers – EPROM/ROM-Based 8-Bit Microcontroller Series

TLC
TLC156
CLRA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Clear ACC
CLRA
None
00h à ACC;
1àZ
Z
The ACC register is cleared. Zero bit (Z) is set.
1
CLRR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Clear R
CLRR R
0 ≤ R ≤ 63
00h à R;
1àZ
Z
The contents of register ‘R’are cleared and the Z bit is set.
1
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Clear Watchdog Timer
CLRWDT
None
00h à WDT;
00h à WDT prescaler (if assigned);
1 à TO ;
1 à PD
TO _, PD
The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is
assigned to the WDT and not Timer0. Status bitsTO and PD are set.
1
COMR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Complement R
COMR R, d
0 ≤ R ≤ 63
d ∈ [0,1]
R à dest
Z
The contents of register ‘R’are complemented. If ‘d’is 0 the result is stored in the ACC
register. If ‘d’is 1 the result is stored back in register ‘R’.
1
DAA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Adjust ACC’s data format from HEX to DEC
DAA
None
ACC(hex) à ACC(dec)
C
Convert the ACC data from hexadecimal to decimal format after any addition
operation and restored to ACC.
1
Rev0.95 Nov 20, 2003
P.2/TLC156