DRP3510 Datasheet, PDF (8/30 Pages) List of Unclassifed Manufacturers – Digital Receiver Front-end

DRX 3960A
ADVANCE INFORMATION
2. Functional Description
2.1. Input Amplifier with TOP Setting
The first block of the DRX 3960A is a low-noise pre-
amplifier. It has a setable gain between 0 and 20 dB for
setting the Tuner take Over Point voltage (TOP). This
adjustment is responsible for optimal tuner operation.
Note: The TOP is the tuner input voltage at which the
IF circuit (e.g. the DRX 3960A) begins to reduce the
tuner gain. Thus, above this voltage the tuner output
voltage remains nearly constant. Of course, the gain of
the tuner is only allowed to be reduced if the S/N is suf-
ficiently high. A level of 60...70 dBµV at the antenna
input is a typical value for the starting point of gain
reduction.
2.2. Carrier Recovery
A digital PLL performs the tracking of the picture car-
rier and therefore synchronous demodulation.
The lock in range refers to the desired IF frequency
which is chosen according to the programmed TV
standard (e.g. 32.9 MHz at L’ or 38.9 MHz at all other
standards).
The PLL incorporates its own AFC function and pro-
vides the frequency offset from the desired IF fre-
quency for external use (CR_FREQ). A special digital
validation algorithm allows long frequency lock at
100% modulation. Additionally, the PLL aligns the digi-
tal calculated Nyquist slope to the picture carrier fre-
quency.
Due to its digital implementation, the carrier recovery
is absolutely offset-free, alignment-free, drift-free, and
quartz-accurate.
2.3. Channel Filtering and Audio/Video Splitting
According to the selected standard, channel filtering
(suppression of not wanted signals) is performed inter-
nally by digital filters. These filters additionally sepa-
rate the video and sound components of the desired
channel and transfer them to the according output. The
processing is competitive to conventional QSS sys-
tems.
2.4. Video and Tuner AGC
The video AGC controls the CVBS amplitude to a
given value (VID_AMP). This value may be set via I²C
bus.
In positive modulation mode, an adaptive back porch
control (BPC) is activated. If the detected BP reference
8
is higher than 38% of the CVBS amplitude, or lower
than 17%, it is set to the according limit.
If the video AGC gain is to low, the tuner AGC
increases its output current. Thus, the tuner reduces
its gain.
The actual gain value of both control loops can be read
out (VID_GAIN, TAGC_I) as information about the
input signal strength.
2.5. Group Delay Equalizing
The group delay is set to compensate the pre-distor-
tion of the transmitter. Additionally, the standard set-
tings can be changed by means of four coefficients to
optimize the complete signal path (EQU_0, EQU_1,
EQU_2, EQU_3).
2.6. Peaking
To shape the frequency response, a peaking filter is
implemented. The following figure indicates the possi-
ble frequency responses:
Video Response [dB]
10
7.5
5
2.5
0
-2.5
-5
-7.5
1
2
3
Freq⁴uency [MHz⁵]
Fig. 2–1: Peaking filter frequency response
The peaking value is setable via I²C (VID_PEAK).
2.7. SIF AGC
The SIF AGC controls the level of the sound carrier
output. Four different reference amplitude values are
available (SIF_REF) .
The actual gain (SIF_GAIN) can be read out and set
via I²C.
According to the standard, the time constant is
switched to FM/NICAM (fast AGC) or AM (slow AGC).
2.8. Output Ports
Six general purpose output ports can be switched to
high or low level.
Micronas