DRP3510 Datasheet, PDF (14/30 Pages) List of Unclassifed Manufacturers – Digital Receiver Front-end

DRX 3960A
4.1.4. Proposals for General DRX 3960A I²C Telegrams
4.1.4.1. Symbols
daw
write device address (82_hex, 86_hex or 8A_hex)
dar
read device address (83_hex, 87_hex or 8B_hex)
<
Start Condition
>
Stop Condition
aa
Address Byte
dd
Data Byte
4.1.4.2. Write Telegrams
<daw 00 d0 00>
<daw 10 aa aa dd dd>
write to CONTROL register
write data into DRX
4.1.4.3. Read Telegrams
<daw 11 aa aa <dar dd dd>
read data from DRX
ADVANCE INFORMATION
4.2. List of Control Registers
Table 4–5: List of Control Registers
Write Register
Address Bits
(hex)
I²C Subaddress = 03_hex ; Register is not readable.
Output ports
no
[5:0]
I²C Subaddress = 10_hex ; Register are not readable.
Standard select
00 20
[11:0]
Level settings
10 01
[9:0]
Reference divider
10 10
[8:0]
Tuner take over point
Equalizer Coe. 0
Equalizer Coe. 1
Equalizer Coe. 2
Equalizer Coe. 3
10 12
10 70
10 71
10 72
10 73
[3:0]
[9:0]
[8:0]
[8:0]
[8:0]
Description
Output level of Ports
Transmission standard
[VID_PEAK, SIF_REF, VID_AMP]
[for 4 MHz, 13 MHz, 20.25 MHz, 27 MHz or other
REF_SW = high
REF_SW = low]
[0 dB ... 20 dB]
Equalizer coefficient
Equalizer coefficient
Equalizer coefficient
Equalizer coefficient
Reset
(hex)
0
01 03
10D
0CA
3
025
197
0C5
12E
14
Micronas