DRP3510 Datasheet, PDF (12/30 Pages) List of Unclassifed Manufacturers – Digital Receiver Front-end

DRX 3960A
ADVANCE INFORMATION
4.1.2. Description of CONTROL Register
Table 4–3: CONTROL as a Write Register
Name
Subaddress
CONTROL 00_hex
Bit[15] (MSB)
1 : RESET
0 : normal
Bits[14:0]
0
Table 4–4: CONTROL as a Read Register
Name
Subaddress Bit[15] (MSB)
Bit>@
BitV>@
CONTROL 00_hex
Reset status after last reading of CONTROL: Internal hardware status: not of interest
0 : no reset occurred
0 : no error occurred
1 : reset occurred
1 : internal error occurred
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be
read once to be reset.
12
Micronas