DRP3510 Datasheet, PDF (21/30 Pages) List of Unclassifed Manufacturers – Digital Receiver Front-end

ADVANCE INFORMATION
DRX 3960A
5.3. Pin Descriptions
Pin 1, AVSS_ADC − Analog ground for ADC
Pin 2, AVDD_ADC − Analog supply for ADC
This pin must be connected to 5 V.
Pin 3, ANATSTX − Reserved for test
This pin should be connected to analog ground.
Pin 4, ANATSTY − Reserved for test
This pin should be connected to analog ground.
Pin 5, AVDD_FE8 − Analog supply for analog front-
end This pin must be connected to 5 V.
Pin 6, AVSS_FE8 − Analog ground for analog front-
end
Pin 7, AVSS_FE40 − Analog ground for IF input cir-
cuitry.
The layout of the IF input should be symmetrical with
respect to AVDD_FE40.
Pin 8, IFINX − Balanced IF input X
This pin must be connected to SAW output. SAW has
to be placed as close as possible. The layout of the IF
input should be symmetrical with respect to
AVDD_FE40.
Pin 9, AVDD_FE40 − Analog supply for IF input cir-
cuitry
This pin must be connected to 5 V. The layout of the IF
input should be symmetrical with respect to
AVDD_FE40.
Pin 10, IFINX − Balanced IF input Y
This pin must be connected to SAW output. SAW has
to be placed as close as possible. The layout of the IF
input should be symmetrical with respect to
AVDD_FE40.
Pin 11, AVSS_FE40 − Analog ground for IF input cir-
cuitry
The layout of the IF input should be symmetrical with
respect to AVDD_FE40.
Pin 12, AVDD_SYN − Analog supply for clock synthe-
sizer. This pin must be connected to 5 V.
Pin 13, AVSS_SYN − Analog ground for clock synthe-
sizer.
Pin 14, SHIELD − Analog ground for shielding analog
from digital part.
Pin 15,16,17, TEST0 1 2 − Pins for factory test
Pin 18, CVBS − Video output
Output level is set via I²C-Bus. An appropriate video
processor (e.g. VPC etc.) has to be connected to that
pin.
Pin 19, REF_SW− Reference frequency switch. This
input defines the default setting of the reference divider
after POR. For 20.25 MHz applications it has to be
connected to ground, for applications with higher fre-
quencies than 20.25 MHz it must be connected to
3.3 V.
Pin 20, SIF − 2nd sound IF ouput
Output level is set via I2C-Bus. An appropriate sound
processor (e.g. MSP) has to be connected to that pin.
Pin 21, AVDD_DAC − Analog supply for the analog
output DACs
This pin must be connected to 5 V.
Pin 22, AVSS_DAC − Analog Ground for the analog
output DACs
This pin must be connected to ground.
Pin 23, TEST_EN − Test Enable pin
This pin enables factory test modes. For normal opera-
tion it must be connected to ground.
Pin 24, RESET − Reset input
For normal operation, a high level is required. A low
level resets the DRX 3960A.
Pin 25, 26, I2C_SDA, I2C_SCL− I2C control bus data
and clock
Pin 27, DVDD_CAP − Digital supply pin
This pin has to be connected to 3.3 V according to the
application circuit.
Pin 28, DVDD − Digital supply pin
This pin has to be connected to 3.3 V according to the
application circuit.
Pin 29, DVSS − Digital ground pin
This pin has to be connected to digital ground accord-
ing to the application circuit.
Pin 30, DVSS_CAP − Digital ground pin
This pin has to be connected according to the applica-
tion circuit.
Pin 31, 32, 34, 35, 36, 38, PORT0 1 2 3 4 5 − General
purpose output ports
Their states are controlled via I2C bus.
Pin 33, TUNER_AGC − This pin controls the delayed
tuner AGC. As it is a noise-shaped-I-DAC output, it has
to be connected according to the application circuit.
Micronas
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