DRP3510 Datasheet, PDF (13/30 Pages) List of Unclassifed Manufacturers – Digital Receiver Front-end

ADVANCE INFORMATION
DRX 3960A
4.1.3. Protocol Description
Write protocol
S write Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte- ACK data-byte ACK P
device
high
low
high
low
address
Read protocol
S write Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK S read Wait ACK data-byte- ACK data-byte NAK P
device
high
low
device
high
low
address
address
Write to Control or Test Registers
S write Wait ACK sub-addr ACK data-byte ACK data-byte ACK P
device
high
low
address
Write to Port Registers
S write Wait ACK sub-addr ACK data-byte ACK P
device
address
Note: S =
P=
ACK =
NAK =
Wait =
I²C bus Start Condition from master
I²C bus Stop Condition from master
Acknowledge-Bit: LOW on I2C_DA from slave (= DRX, light gray)
or master (= controller dark gray)
Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’
or from DRX indicating internal error state
I²C clock line is held low, while the DRX is processing the I²C command. This waiting time is
max. 1 ms
I2C_DA
1
0
S
P
I2C_CL
Fig. 4–1: I²C bus protocol (MSB first; data must be stable while clock is high)
Micronas
13